关于NVIC中断，分组，设置优先级

烂冬瓜 · 发表于 2016-11-23 21:00:37

就是想问下关于NVIC结构体下的那几个寄存器哪里查资料？
提供的《stm32中文参考手册》找不到相应的寄存器的么。
typedef struct
{
  __IO uint32_t ISER[8];                   /*!< Offset: 0x000  Interrupt Set Enable Register          */
   uint32_t RESERVED0[24];
  __IO uint32_t ICER[8];                   /*!< Offset: 0x080  Interrupt Clear Enable Register       */
   uint32_t RSERVED1[24];
  __IO uint32_t ISPR[8];                   /*!< Offset: 0x100  Interrupt Set Pending Register       */
   uint32_t RESERVED2[24];
  __IO uint32_t ICPR[8];                   /*!< Offset: 0x180  Interrupt Clear Pending Register       */
   uint32_t RESERVED3[24];
  __IO uint32_t IABR[8];                   /*!< Offset: 0x200  Interrupt Active bit Register          */
   uint32_t RESERVED4[56];
  __IO uint8_t  IP[240];                   /*!< Offset: 0x300  Interrupt Priority Register (8Bit wide) */
   uint32_t RESERVED5[644];
  __O  uint32_t STIR;                      /*!< Offset: 0xE00  Software Trigger Interrupt Register    */
}  NVIC_Type;

typedef struct
{
  __I  uint32_t CPUID;                      /*!< Offset: 0x00  CPU ID Base Register                               */
  __IO uint32_t ICSR;                      /*!< Offset: 0x04  Interrupt Control State Register                   */
  __IO uint32_t VTOR;                      /*!< Offset: 0x08  Vector Table Offset Register                         */
  __IO uint32_t AIRCR;                      /*!< Offset: 0x0C  Application Interrupt / Reset Control Register       */
  __IO uint32_t SCR;                         /*!< Offset: 0x10  System Control Register                            */
  __IO uint32_t CCR;                         /*!< Offset: 0x14  Configuration Control Register                      */
  __IO uint8_t  SHP[12];                   /*!< Offset: 0x18  System Handlers Priority Registers (4-7, 8-11, 12-15) */
  __IO uint32_t SHCSR;                      /*!< Offset: 0x24  System Handler Control and State Register          */
  __IO uint32_t CFSR;                      /*!< Offset: 0x28  Configurable Fault Status Register                   */
  __IO uint32_t HFSR;                      /*!< Offset: 0x2C  Hard Fault Status Register                         */
  __IO uint32_t DFSR;                      /*!< Offset: 0x30  Debug Fault Status Register                         */
  __IO uint32_t MMFAR;                      /*!< Offset: 0x34  Mem Manage Address Register                         */
  __IO uint32_t BFAR;                      /*!< Offset: 0x38  Bus Fault Address Register                         */
  __IO uint32_t AFSR;                      /*!< Offset: 0x3C  Auxiliary Fault Status Register                      */
  __I  uint32_t PFR[2];                      /*!< Offset: 0x40  Processor Feature Register                         */
  __I  uint32_t DFR;                         /*!< Offset: 0x48  Debug Feature Register                               */
  __I  uint32_t ADR;                         /*!< Offset: 0x4C  Auxiliary Feature Register                         */
  __I  uint32_t MMFR[4];                   /*!< Offset: 0x50  Memory Model Feature Register                      */
  __I  uint32_t ISAR[5];                   /*!< Offset: 0x60  ISA Feature Register                               */
} SCB_Type;

像这两个结构体，都是关于中断初始化里的。这个在哪里能查看详细信息？