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楼主 |
发表于 2014-11-21 19:56:52
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SSD2805+SSD1963+HX8379A initial code 如下:參考一下
/***********************************************
* Module initial
***********************************************/
void DISP_INIT(void)
{
//*********POWER ON &RESET DISPLAY OFF
DISP_COMMAND(0xE2);//PLL multiplier, set  LL clock to 120M
DISP_WRITE(0x36); //N=0x36 for 6.5M, 0x23 for 10M crystal
DISP_WRITE(0x08);
DISP_WRITE(0x09);
DISP_COMMAND(0xe0);//  LL enable
DISP_WRITE(0x01);
DELAY(5);
DISP_COMMAND(0xe0);
DISP_WRITE(0x03);
DELAY(5);
DISP_COMMAND(0x01);
DELAY(5);
DISP_COMMAND(0xe6);//PLL setting for  CLK, depends on resolution
DISP_WRITE(0x05); //01 6.75M
DISP_WRITE(0x20); //8f
DISP_WRITE(0x0e); //00
DISP_COMMAND(0xB0); //LCD SPECIFICATION
DISP_WRITE(0x04);
DISP_WRITE(0x00);
DISP_WRITE((HDP>>8)&0X00FF); //Set HDP
DISP_WRITE((HDP&0X00FF));
DISP_WRITE(((VDP>>8)&0X00FF)); //Set VDP
DISP_WRITE((VDP&0X00FF));
DISP_WRITE(0x00);
DELAY(5);
DISP_COMMAND(0xB4); //HSYNC
DISP_WRITE(((HT>>8)&0X00FF)); //Set HT
DISP_WRITE((HT&0X00FF));
DISP_WRITE((HPS>>8)&0X00FF); //Set HPS
DISP_WRITE((HPS&0X00FF));
DISP_WRITE(HPW); //Set HPW
DISP_WRITE(((LPS>>8)&0X00FF)); //SetLPS
DISP_WRITE((LPS&0X00FF));
DISP_WRITE(0x00);
DISP_COMMAND(0xB6); //VSYNC
DISP_WRITE(((VT>>8)&0X00FF)); //Set VT
DISP_WRITE((VT&0X00FF));
DISP_WRITE(((VPS>>8)&0X00FF)); //Set VPS
DISP_WRITE((VPS&0X00FF));
DISP_WRITE((VPW)); //Set VPW
DISP_WRITE(((FPS>>8)&0X00FF)); //Set FPS
DISP_WRITE((FPS&0X00FF));
DISP_COMMAND(0x2A);
DISP_WRITE(0);
DISP_WRITE(0);
DISP_WRITE(HDP>>8);
DISP_WRITE(HDP&0x00ff);
DISP_COMMAND(0x2b);
DISP_WRITE(0);
DISP_WRITE(0);
DISP_WRITE(VDP>>8);
DISP_WRITE(VDP&0x00ff);
DISP_COMMAND(0x36);//rotation
DISP_WRITE(0x00);
DISP_COMMAND(0xf0);//pixel data interface
DISP_WRITE(0x03); //16-bit (565 format)
/****************SET BL  MW*****************/
/*wr_com8080_16(0x00,0xBE);//set  WM for B/L
DISP_WRITE(0x06);
DISP_WRITE(0xF0);
DISP_WRITE(0x01);
DISP_WRITE(0xF0);
DISP_WRITE(0x00);
DISP_WRITE(0x00);
DISP_COMMAND(0xBA);
DISP_WRITE(0x00);*/
/*************************************/
DISP_COMMAND(0x29);//display on
}
void SSD2805_INIT()
{
//Enable  LL (Register[0xB9]=0x0001)
MLCD_IndexReg(0XB9);
MLCD_RegSet(0X00);
MLCD_RegSet(0X00);
//Set  LL (Register[0xBA]=0x311F)
MLCD_IndexReg(0XBA);
MLCD_RegSet(0X51);
MLCD_RegSet(0X31);
MLCD_IndexReg(0xBB);
MLCD_RegSet(0x03);
MLCD_RegSet(0x00);
//Enable  LL (Register[0xB9]=0x0001)
MLCD_IndexReg(0XB9);
MLCD_RegSet(0X01);
MLCD_RegSet(0X00);
DELAY(50);
// while(1);
// Configure to DCS  acket Write Mode, using HS mode
// (Low  ower)
// Register[0xB7]=0x0210
MLCD_IndexReg(0xB7);
MLCD_RegSet(0x10);
MLCD_RegSet(0x01);
HX8379A_INIT();
}
void HX8379A_INIT()
{
RegSet_Mun(4);
MLCD_IndexReg(0xBF);
MLCD_RegSet(0xB9);
MLCD_RegSet(0xFF);
MLCD_RegSet(0x83);
MLCD_RegSet(0x79);
HX8379A_WC_RESET();
RegSet_Mun(3);
MLCD_IndexReg(0xBF);
MLCD_RegSet(0xBA);
MLCD_RegSet(0x51);
MLCD_RegSet(0x93);
HX8379A_WC_RESET();
RegSet_Mun(20);
MLCD_IndexReg(0xBF);
MLCD_RegSet(0xB1);
MLCD_RegSet(0x00);
MLCD_RegSet(0x50);
MLCD_RegSet(0x44);
MLCD_RegSet(0xE8);
MLCD_RegSet(0x94);
MLCD_RegSet(0x08);
MLCD_RegSet(0x11);
MLCD_RegSet(0x12);
MLCD_RegSet(0x72);
MLCD_RegSet(0x28);
MLCD_RegSet(0x30);
MLCD_RegSet(0x9A);
MLCD_RegSet(0x1A);
MLCD_RegSet(0x42);
MLCD_RegSet(0x08);
MLCD_RegSet(0x76);
MLCD_RegSet(0xF1);
MLCD_RegSet(0x00);
MLCD_RegSet(0xE6);
HX8379A_WC_RESET();
RegSet_Mun(14);
MLCD_IndexReg(0xBF);
MLCD_RegSet(0xB2); //B2);
MLCD_RegSet(0x00); //00);
MLCD_RegSet(0x00); //00);
MLCD_RegSet(0x3C); //3C);
MLCD_RegSet(0x07); //08);
MLCD_RegSet(0x02); //0C);
MLCD_RegSet(0x19); //19);
MLCD_RegSet(0x22); //22);
MLCD_RegSet(0x00); //00);
MLCD_RegSet(0xFF); //FF);
MLCD_RegSet(0x07); //08);
MLCD_RegSet(0x02); //0C);
MLCD_RegSet(0x19); //19);
MLCD_RegSet(0x20); //20);
HX8379A_WC_RESET();
RegSet_Mun(32);
MLCD_IndexReg(0xBF);
MLCD_RegSet(0xB4); //B4);
MLCD_RegSet(0x82); //82);
MLCD_RegSet(0x00); //00);
MLCD_RegSet(0x00); //00);
MLCD_RegSet(0x32); //32);
MLCD_RegSet(0x10); //10);
MLCD_RegSet(0x03); //04);
MLCD_RegSet(0x32); //32);
MLCD_RegSet(0x13); //13);
MLCD_RegSet(0x30); //5F);
MLCD_RegSet(0x32); //32);
MLCD_RegSet(0x10); //10);
MLCD_RegSet(0x08); //08);
MLCD_RegSet(0x35); //35);
MLCD_RegSet(0x01); //01);
MLCD_RegSet(0x28); //28);
MLCD_RegSet(0x0E); //07);
MLCD_RegSet(0x37); //37);
MLCD_RegSet(0x00); //00);
MLCD_RegSet(0x34); //30);
MLCD_RegSet(0x08); //08);
MLCD_RegSet(0x3E); //30);
MLCD_RegSet(0x3E); //30);
MLCD_RegSet(0x08); //04);
MLCD_RegSet(0x00); //00);
MLCD_RegSet(0x40); //40);
MLCD_RegSet(0x08); //08);
MLCD_RegSet(0x28); //28);
MLCD_RegSet(0x08); //08);
MLCD_RegSet(0x30); //30);
MLCD_RegSet(0x30); //30);
MLCD_RegSet(0x04); //04);
HX8379A_WC_RESET();
RegSet_Mun(2);
MLCD_IndexReg(0xBF);
MLCD_RegSet(0xCC);
MLCD_RegSet(0x02);
HX8379A_WC_RESET();
RegSet_Mun(48);
MLCD_IndexReg(0xBF);
MLCD_RegSet(0xD5); //D5);
MLCD_RegSet(0x00); //00);
MLCD_RegSet(0x00); //00);
MLCD_RegSet(0x0A); //0A);
MLCD_RegSet(0x00); //00);
MLCD_RegSet(0x01); //01);
MLCD_RegSet(0x05); //05);
MLCD_RegSet(0x00); //00);
MLCD_RegSet(0x00); //00);
MLCD_RegSet(0x18); //18);
MLCD_RegSet(0x88); //88);
MLCD_RegSet(0x99); //99);
MLCD_RegSet(0x88); //88);
MLCD_RegSet(0x01); //01);
MLCD_RegSet(0x45); //45);
MLCD_RegSet(0x88); //88);
MLCD_RegSet(0x88); //88);
MLCD_RegSet(0x01); //01);
MLCD_RegSet(0x45); //45);
MLCD_RegSet(0x23); //23);
MLCD_RegSet(0x67); //67);
MLCD_RegSet(0x88); //88);
MLCD_RegSet(0x88); //88);
MLCD_RegSet(0x88); //88);
MLCD_RegSet(0x88); //88);
MLCD_RegSet(0x88); //88);
MLCD_RegSet(0x88); //88);
MLCD_RegSet(0x88); //88);
MLCD_RegSet(0x99); //99);
MLCD_RegSet(0x54); //54);
MLCD_RegSet(0x10); //10);
MLCD_RegSet(0x88); //88);
MLCD_RegSet(0x88); //88);
MLCD_RegSet(0x76); //76);
MLCD_RegSet(0x32); //32);
MLCD_RegSet(0x54); //54);
MLCD_RegSet(0x10); //10);
MLCD_RegSet(0x88); //88);
MLCD_RegSet(0x88); //88);
MLCD_RegSet(0x88); //88);
MLCD_RegSet(0x88); //88);
MLCD_RegSet(0x88); //88);
MLCD_RegSet(0x00); //00);
MLCD_RegSet(0x00); //00);
MLCD_RegSet(0x00); //00);
MLCD_RegSet(0x00); //00);
MLCD_RegSet(0x00); //00);
MLCD_RegSet(0x00); //00);
HX8379A_WC_RESET();
RegSet_Mun(36);
MLCD_IndexReg(0xBF);
MLCD_RegSet(0xE0);
MLCD_RegSet(0x79);
MLCD_RegSet(0x00);
MLCD_RegSet(0x16);
MLCD_RegSet(0x22);
MLCD_RegSet(0x28);
MLCD_RegSet(0x2A);
MLCD_RegSet(0x3F);
MLCD_RegSet(0x3B);
MLCD_RegSet(0x4C);
MLCD_RegSet(0x09);
MLCD_RegSet(0x10);
MLCD_RegSet(0x10);
MLCD_RegSet(0x15);
MLCD_RegSet(0x17);
MLCD_RegSet(0x15);
MLCD_RegSet(0x16);
MLCD_RegSet(0x13);
MLCD_RegSet(0x18);
MLCD_RegSet(0x00);
MLCD_RegSet(0x16);
MLCD_RegSet(0x22);
MLCD_RegSet(0x29);
MLCD_RegSet(0x29);
MLCD_RegSet(0x3F);
MLCD_RegSet(0x3B);
MLCD_RegSet(0x4C);
MLCD_RegSet(0x09);
MLCD_RegSet(0x10);
MLCD_RegSet(0x11);
MLCD_RegSet(0x14);
MLCD_RegSet(0x17);
MLCD_RegSet(0x16);
MLCD_RegSet(0x16);
MLCD_RegSet(0x12);
MLCD_RegSet(0x17);
HX8379A_WC_RESET();
RegSet_Mun(5);
MLCD_IndexReg(0xBF);
MLCD_RegSet(0xB6);
MLCD_RegSet(0x00);
MLCD_RegSet(0x83);
MLCD_RegSet(0x00);
MLCD_RegSet(0x83);
HX8379A_WC_RESET();
RegSet_Mun(2);
MLCD_IndexReg(0xBF);
MLCD_RegSet(0x35);
MLCD_RegSet(0x01);
HX8379A_WC_RESET();
RegSet_Mun(4);
MLCD_IndexReg(0xBF);
MLCD_RegSet(0xB5);
MLCD_RegSet(0x00);
MLCD_RegSet(0x32);
MLCD_RegSet(0x32);
HX8379A_WC_RESET();
RegSet_Mun(2);
MLCD_IndexReg(0xBF);
MLCD_RegSet(0x3A);
MLCD_RegSet(0x70);
HX8379A_WC_RESET();
RegSet_Mun(1);
MLCD_IndexReg(0xBF);
MLCD_RegSet(0x11);
DELAY(150);
HX8379A_WC_RESET();
RegSet_Mun(1);
MLCD_IndexReg(0xBF);
MLCD_RegSet(0x29);
DELAY(150);
//set PLL Lock Status Enable(Bit 7)
//in Interrupt Control Register
//Register[0xC5]=0x0080
MLCD_IndexReg(0xC5); // Video Mode //
MLCD_RegSet(0x05);
MLCD_RegSet(0x10);
//Vertical and Horizontal Sync Period, Register[0xB1]=0x0B27
MLCD_IndexReg(0xB1);
MLCD_RegSet(0x05);
MLCD_RegSet(0x05);
//Vertical and Horizontal back porch ,Register[0xB2]=0x806
MLCD_IndexReg(0xB2);
MLCD_RegSet(0x02);
MLCD_RegSet(0x0D);
//Vertical and horizontal front porch ,Register[0xB3]=0x0C28
MLCD_IndexReg(0xB3);
MLCD_RegSet(0x0A);
MLCD_RegSet(0x02);
//Horizontal Active Period ,Register[0xB4]=0x0140
MLCD_IndexReg(0xB4);
MLCD_RegSet(0xE0);
MLCD_RegSet(0x01);
//Vertical Active Period ,Register[0xB5]=0x01E0
MLCD_IndexReg(0xB5);
MLCD_RegSet(0x20);
MLCD_RegSet(0x03);
//Set NON-BURST Mode with Sync Event 18bpp
//Register[0xB6]=0x0021
MLCD_IndexReg(0xB6);
MLCD_RegSet(0x21);
MLCD_RegSet(0x00);
//Disable PLL
//Register[0xB9]=0x0000
MLCD_IndexReg(0xB9);
MLCD_RegSet(0x00);
MLCD_RegSet(0x00);
//Change Clock Source as PCLK (for non-burst mode)
//Register[0xB7]=0x0230
// MLCD_IndexReg(0xB7);
// MLCD_RegSet(0x30);
// MLCD_RegSet(0x02);
//Set PLL multiplier
//Register[0xBA]=0x102F
MLCD_IndexReg(0xBA);
MLCD_RegSet(0x2A);
MLCD_RegSet(0x20);
// MLCD_IndexReg(0xBB);
// MLCD_RegSet(0x03);
// MLCD_RegSet(0x00);
//Re-enable PLL, Register[0xB9]=0x0001
MLCD_IndexReg(0XB9);
MLCD_RegSet(0X01);
MLCD_RegSet(0X00);
DELAY(50);
/*
//HS TX Timer1 (MIPI Signal), Register[0xCF]=0x0000
MLCD_IndexReg(0xCF);
MLCD_RegSet(0x00);
MLCD_RegSet(0x00);
//HS TX Timer2 (MIPI Signal), Register[0xD0]=0x8000
MLCD_IndexReg(0xD0);
MLCD_RegSet(0x00);
MLCD_RegSet(0x80);
//Set endian and color order(panel driver dependent)
//Register[0xD6]=0x0005
MLCD_IndexReg(0xD6);
MLCD_RegSet(0x01);
MLCD_RegSet(0x00);
//Set VC1=1, Register[0xB8]=0x0049
MLCD_IndexReg(0xB8);
MLCD_RegSet(0x49);
MLCD_RegSet(0x00);*/
//Enable Video Mode (Start Video Data Transmission)
MLCD_IndexReg(0xB7);
MLCD_RegSet(0x39);
MLCD_RegSet(0x01);
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