你说的把图片数据存进sram,是通过软件FSMC_SRAM_WriteBuffer()写进去,还是通过调keil直接可以把数组下载到sram?
数组加了const之后是下载到了哪里?
下面这个是库里面关于DMA读写fsmc的例子,只有sram的地址,为什么可以和fsmc连接,,
还是想快速刷屏,求代码指点
#define BufferSize 32
#define Bank1_SRAM3_ADDR ((uint32_t)0x68000000)
volatile TestStatus TransferStatus;
const uint32_t SRC_Const_Buffer[BufferSize]= {
0x01020304,0x05060708,0x090A0B0C,0x0D0E0F10,
0x11121314,0x15161718,0x191A1B1C,0x1D1E1F20,
0x21222324,0x25262728,0x292A2B2C,0x2D2E2F30,
0x31323334,0x35363738,0x393A3B3C,0x3D3E3F40,
0x41424344,0x45464748,0x494A4B4C,0x4D4E4F50,
0x51525354,0x55565758,0x595A5B5C,0x5D5E5F60,
0x61626364,0x65666768,0x696A6B6C,0x6D6E6F70,
0x71727374,0x75767778,0x797A7B7C,0x7D7E7F80};
uint8_t DST_Buffer[4*BufferSize], Idx = 0;
TestStatus Buffercmp(const uint32_t* pBuffer, uint32_t* pBuffer1, uint16_t BufferLength);
DMA_InitTypeDef DMA_InitStructure;
/* Write to FSMC -----------------------------------------------------------*/
/* DMA2 channel5 configuration */
DMA_DeInit(DMA2_Channel5);
DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)SRC_Const_Buffer;
DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)Bank1_SRAM3_ADDR;
DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
DMA_InitStructure.DMA_BufferSize = 32;
DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Enable;
DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Word;
DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Word;
DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
DMA_InitStructure.DMA_Priority = DMA_Priority_High;
DMA_InitStructure.DMA_M2M = DMA_M2M_Enable;
DMA_Init(DMA2_Channel5, &DMA_InitStructure);
/* Enable DMA2 channel5 */
DMA_Cmd(DMA2_Channel5, ENABLE);
/* Check if DMA2 channel5 transfer is finished */
while(!DMA_GetFlagStatus(DMA2_FLAG_TC5));
/* Clear DMA2 channel5 transfer complete flag bit */
DMA_ClearFlag(DMA2_FLAG_TC5);
/* Read from FSMC ----------------------------------------------------------*/
/* Destination buffer initialization */
for(Idx=0; Idx<128; Idx++) DST_Buffer[Idx]=0;
/* DMA1 channel3 configuration */
DMA_DeInit(DMA1_Channel3);
DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)Bank1_SRAM3_ADDR;
DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)DST_Buffer;
DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
DMA_InitStructure.DMA_BufferSize = 128;
DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Enable;
DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
DMA_InitStructure.DMA_Priority = DMA_Priority_High;
DMA_InitStructure.DMA_M2M = DMA_M2M_Enable;
DMA_Init(DMA1_Channel3, &DMA_InitStructure);
/* Enable DMA1 channel3 */
DMA_Cmd(DMA1_Channel3, ENABLE);
/* Check if DMA1 channel3 transfer is finished */
while(!DMA_GetFlagStatus(DMA1_FLAG_TC3));
/* Clear DMA1 channel3 transfer complete flag bit */
DMA_ClearFlag(DMA1_FLAG_TC3); |