enable_i2c0_pin_mux();
i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
if (read_eeprom(&header) < 0)
puts("Could not get board ID.\n");
if (board_is_evm_sk(&header))
return &dpll_ddr_evm_sk;
else if (board_is_bone_lt(&header)||board_is_wd335x(&header))
return &dpll_ddr_bone_black;
else if (board_is_evm_15_or_later(&header))
return &dpll_ddr_evm_sk;
else
return &dpll_ddr;
}
说明：我的板子的用的内存的DDR3可以跑到400M所以尝试一下400MHz，可选择dpll_ddr_bone_black的参数表。
将函数void am33xx_spl_board_init(void)修改成如下
void am33xx_spl_board_init(void)
{
struct am335x_baseboard_id header;
int mpu_vdd;
if (read_eeprom(&header) < 0)
puts("Could not get board ID.\n");
/* Get the frequency */
dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
if (board_is_bone(&header) || board_is_bone_lt(&header)||board_is_wd335x(&header)) {
/* BeagleBone PMIC Code */
int usb_cur_lim;
/*
* Only perform PMIC configurations if board rev > A1
* on Beaglebone White
*/
if (board_is_bone(&header) && !strncmp(header.version,
"00A1", 4))
return;
if (i2c_probe(TPS65217_CHIP_PM))
return;
/*
* On Beaglebone White we need to ensure we have AC power
* before increasing the frequency.
*/
if (board_is_bone(&header)) {
uchar pmic_status_reg;
if (tps65217_reg_read(TPS65217_STATUS,
&pmic_status_reg))
return;
if (!(pmic_status_reg & TPS65217_PWR_SRC_AC_BITMASK)) {
puts("No AC power, disabling frequency switch\n");
return;
}
}
/*
* Override what we have detected since we know if we have
* a Beaglebone Black it supports 1GHz.
*/
if (board_is_bone_lt(&header)||board_is_wd335x(&header))
dpll_mpu_opp100.m = MPUPLL_M_1000;
/*
* Increase USB current limit to 1300mA or 1800mA and set
* the MPU voltage controller as needed.
*/
if (dpll_mpu_opp100.m == MPUPLL_M_1000) {
usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
} else {
usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
}
if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
TPS65217_POWER_PATH,
usb_cur_lim,
TPS65217_USB_INPUT_CUR_LIMIT_MASK))
puts("tps65217_reg_write failure\n");
/* Set DCDC3 (CORE) voltage to 1.125V */
if (tps65217_voltage_update(TPS65217_DEFDCDC3,
TPS65217_DCDC_VOLT_SEL_1125MV)) {
puts("tps65217_voltage_update failure\n");
return;
}
/* Set CORE Frequencies to OPP100 */
do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
/* Set DCDC2 (MPU) voltage */
if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
puts("tps65217_voltage_update failure\n");
return;
}
/*
* Set LDO3, LDO4 output voltage to 3.3V for Beaglebone.
* Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black.
*/
if (board_is_bone(&header)) {
if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
TPS65217_DEFLS1,
TPS65217_LDO_VOLTAGE_OUT_3_3,
TPS65217_LDO_MASK))
puts("tps65217_reg_write failure\n");
} else {
if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
TPS65217_DEFLS1,
TPS65217_LDO_VOLTAGE_OUT_1_8,
TPS65217_LDO_MASK))
puts("tps65217_reg_write failure\n");
}
if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
TPS65217_DEFLS2,
TPS65217_LDO_VOLTAGE_OUT_3_3,
TPS65217_LDO_MASK))
puts("tps65217_reg_write failure\n");
} else {
int sil_rev;
/*
* The GP EVM, IDK and EVM SK use a TPS65910 PMIC. For all
* MPU frequencies we support we use a CORE voltage of
* 1.1375V. For MPU voltage we need to switch based on
* the frequency we are running at.
*/
if (i2c_probe(TPS65910_CTRL_I2C_ADDR))
return;
/*
* Depending on MPU clock and PG we will need a different
* VDD to drive at that speed.
*/
sil_rev = readl(&cdev->deviceid) >> 28;
mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev,
dpll_mpu_opp100.m);
/* Tell the TPS65910 to use i2c */
tps65910_set_i2c_control();
/* First update MPU voltage. */
if (tps65910_voltage_update(MPU, mpu_vdd))
return;
/* Second, update the CORE voltage. */
if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3))
return;
/* Set CORE Frequencies to OPP100 */
do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
}
/* Set MPU Frequency to what we detected now that voltages are set */
do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
}
说明：此部分主要初始化电源相关的。
将函数void sdram_init(void)修改成如下
void sdram_init(void)
{
__maybe_unused struct am335x_baseboard_id header;
if (read_eeprom(&header) < 0)
puts("Could not get board ID.\n");
if (board_is_evm_sk(&header)) {
/*
* EVM SK 1.2A and later use gpio0_7 to enable DDR3.
* This is safe enough to do on older revs.
*/
gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
gpio_direction_output(GPIO_DDR_VTT_EN, 1);
}
if (board_is_evm_sk(&header))
config_ddr(303, &ioregs_evmsk, &ddr3_data,
&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
else if (board_is_bone_lt(&header)||board_is_wd335x(&header))
config_ddr(400, &ioregs_bonelt,
&ddr3_beagleblack_data,
&ddr3_beagleblack_cmd_ctrl_data,
&ddr3_beagleblack_emif_reg_data, 0);
else if (board_is_evm_15_or_later(&header))
config_ddr(303, &ioregs_evm15, &ddr3_evm_data,
&ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0);
else
config_ddr(266, &ioregs, &ddr2_data,
&ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
}
说明：这里的内存初始化仍然可以使用beagleblack的参数表。
将函数int board_eth_init(bd_t *bis)修改成如下
int board_eth_init(bd_t *bis)
{
int rv, n = 0;
uint8_t mac_addr[6];
uint32_t mac_hi, mac_lo;
__maybe_unused struct am335x_baseboard_id header;
rv = cpsw_register(&cpsw_data);
if (rv < 0)
printf("Error %d registering CPSW switch\n", rv);
else
n += rv;
#endif
/*
*
* CPSW RGMII Internal Delay Mode is not supported in all PVT
* operating points. So we must set the TX clock delay feature
* in the AR8051 PHY. Since we only support a single ethernet
* device in U-Boot, we only do this for the first instance.
*/
#define AR8051_PHY_DEBUG_ADDR_REG 0x1d
#define AR8051_PHY_DEBUG_DATA_REG 0x1e
#define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5
#define AR8051_RGMII_TX_CLK_DLY 0x100
/2 
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发表于 2016-1-7 13:43:44
发表于 2016-1-7 22:52:48
