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发表于 2019-3-5 16:33:06
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本帖最后由 edmund1234 于 2019-3-5 16:38 编辑
我认真的算了一下
这段是在arm官网找到的
Cortex-M3 TRM (for example, revision 'I') states that the interrupt latency on entry is 12 cycles and the latency on exit is also 12 cycles. This is a typographical error in the Cortex-M3 TRM. The Cortex-M3 has a latency on exit of ten cycles, just like the Cortex-M4.
The processor has three main physical interfaces to its memory system; I-Code and D-Code each accessing addresses below 0x20000000, and System accessing addresses 0x20000000 and higher. The 12 cycle latency requires that a nine cycle stack push can take place on one interface (typically the System interface) in parallel with a six cycle vector table read and interrupt handler fetch on other interfaces (typically I-Code). If these operations cannot be performed in parallel, they will have to be performed one after the other, increasing the latency. The ability to perform these memory accesses in parallel depends upon both the hardware design providing the relevant memory blocks at suitable addresses, and software programming of the location of the vector table, interrupt handler code, and stack in those memories
外部中断信号需要10ns脉冲宽 ~约1个时钟
中断延迟需 12个时钟
压栈 9个时钟
从VECTOR获取中断向量 6个时钟
判断中断的指令 ？建议你把这一部分屏蔽来测试
io翻转的指令周期？用
GPIOE->BSRR = GPIO_BSRR_BS_8; 这一句应是需时5个时钟
EXTI->PR = EXTI_PR_PR6;
GPIOE->BSRR = （GPIO_BSRR_BS_8<<16);
这样更改后一共为36时钟， 即0.5us(500ns)
如果说你的延迟是在这范围内就是合理， 否则就是还有别的错误 |
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