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- 2020-11-5
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大佬们,我使用的是正点原子RK3562J开发板,接入两个SC132GS摄像头模组,当前遇到的问题是两个摄像头同时接入,isp取图失败;
环境:
RK3562J开发板,自制sc132gs转接板,使用2lane模式,目前单个摄像头已驱动成功,两个CSI接口都正常捕获图像,开启rkaiq_3A_server,参数加载生效,画面不再过暗,因此想进行下一步双摄同时抓图。
现象:
接入单个摄像头,MIPI0和MIPI1两个接口都可以出图,我修改dts配置两个通路来接入两个摄像头,因为是两个I2C硬件,因此sc132gs配置的地址是一样的都是0x30,两个摄像头同时接入后,不开rkaiq_3A_server,捕获任意一个摄像头都失败;
开发板启动后第一次捕获MIPI0,dmesg输出:
- [ 13.060620] rkisp_hw ff3f0000.isp: set isp clk = 297000000Hz
- [ 13.062758] rkcif-mipi-lvds: stream[0] start streaming
- [ 13.063476] rkcif-mipi-lvds: Allocate dummy buffer, size: 0x002a3000
- [ 13.063723] rockchip-mipi-csi2 mipi0-csi2: stream on, src_sd: 00000000258714a2, sd_name:rockchip-csi2-dphy1
- [ 13.063739] rockchip-mipi-csi2 mipi0-csi2: stream ON
- [ 13.063782] rockchip-csi2-dphy1: dphy1, data_rate_mbps 360
- [ 13.063809] rockchip-csi2-dphy csi2-dphy1: csi2_dphy_s_stream stream on:1, dphy1, ret 0
- [ 13.063822] sc132gs 4-0030: sc132gs_s_stream: on: 1, 1080x1280@30
- [ 13.128627] sc132gs 4-0030: set reg done, send startstream
- [ 13.135949] rkcif-mipi-lvds: stream[0] start stopping, total mode 0x1, cur 0x1
- [ 13.213371] rockchip-mipi-csi2 mipi0-csi2: stream off, src_sd: 00000000258714a2, sd_name:rockchip-csi2-dphy1
- [ 13.213410] rockchip-mipi-csi2 mipi0-csi2: stream OFF
- [ 13.213434] rockchip-csi2-dphy csi2-dphy1: csi2_dphy_s_stream_stop stream stop, dphy1
- [ 13.213452] rockchip-csi2-dphy csi2-dphy1: csi2_dphy_s_stream stream on:0, dphy1, ret 0
- [ 13.213478] sc132gs 4-0030: sc132gs_s_stream: on: 0, 1080x1280@30
- [ 13.214176] rkcif-mipi-lvds: stream[0] stopping finished, dma_en 0x0
- select timeout
复制代码
再次抓同一个节点,报错:
- [ 147.170311] rkisp-vir0: waiting on params stream on event timeout
复制代码 但此时抓cif节点是可以捕获到数据的。
已确认的事:
两个摄像头I2C识别正常,通过逻辑分析仪抓I2C通信正常。
驱动代码使用的kernel6.1中sc132gs.c,无修改。
dts如下:- &i2c4 {
- status = "okay";
- sc132gs_0: sc132gs_0@30 {
- compatible = "smartsens,sc132gs";
- reg = <0x30>;
- clocks = <&ext_cam1_clk>;
- clock-names = "xvclk";
- pwdn-gpios = <&gpio3 RK_PB5 GPIO_ACTIVE_HIGH>;
- // reset-gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_LOW>;
- rockchip,camera-module-index = <0>;
- rockchip,camera-module-facing = "left";
- rockchip,camera-module-name = "CHRTC-SC132GS";
- rockchip,camera-module-lens-name = "2lane";
- port {
- sc132gs_out0: endpoint {
- remote-endpoint = <&mipi_dphy1_sc132gs>;
- data-lanes = <1 2>;
- };
- };
- };
- };
- &i2c5 {
- status = "okay";
- sc132gs_1: sc132gs_1@30 {
- compatible = "smartsens,sc132gs";
- reg = <0x30>;
- clocks = <&ext_cam2_clk>;
- clock-names = "xvclk";
- pwdn-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
- // reset-gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_LOW>;
- rockchip,camera-module-index = <1>;
- rockchip,camera-module-facing = "right";
- rockchip,camera-module-name = "CHRTC-SC132GS";
- rockchip,camera-module-lens-name = "2lane";
- port {
- sc132gs_out1: endpoint {
- remote-endpoint = <&mipi_dphy4_sc132gs>;
- data-lanes = <1 2>;
- };
- };
- };
- };
- &csi2_dphy1 {
- status = "okay";
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
- port@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
- mipi_dphy1_sc132gs: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&sc132gs_out0>;
- data-lanes = <1 2>;
- };
- };
- port@1 {
- reg = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
- csidphy1_out: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&mipi0_csi2_input>;
- };
- };
- };
- };
- &csi2_dphy4 {
- status = "okay";
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
- port@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
- mipi_dphy4_sc132gs: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&sc132gs_out1>;
- data-lanes = <1 2>;
- };
- };
- port@1 {
- reg = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
- csidphy4_out: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&mipi2_csi2_input>;
- };
- };
- };
- };
- &csi2_dphy0_hw {
- status = "okay";
- };
-
- &csi2_dphy1_hw {
- status = "okay";
- };
- &mipi0_csi2 {
- status = "okay";
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
- port@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
- mipi0_csi2_input: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&csidphy1_out>;
- };
- };
- port@1 {
- reg = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
- mipi0_csi2_output: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&cif_mipi_in0>;
- };
- };
- };
- };
- &mipi2_csi2 {
- status = "okay";
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
- port@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
- mipi2_csi2_input: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&csidphy4_out>;
- };
- };
- port@1 {
- reg = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
- mipi2_csi2_output: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&cif_mipi_in2>;
- };
- };
- };
- };
- &rkcif_mipi_lvds {
- status = "okay";
- port {
- cif_mipi_in0: endpoint {
- remote-endpoint = <&mipi0_csi2_output>;
- };
- };
- };
- &rkcif_mipi_lvds2 {
- status = "okay";
- port {
- cif_mipi_in2: endpoint {
- remote-endpoint = <&mipi2_csi2_output>;
- };
- };
- };
- &rkcif_mipi_lvds_sditf {
- status = "okay";
- port {
- mipi_lvds_sditf: endpoint {
- remote-endpoint = <&isp_vir0>;
- };
- };
- };
- &rkcif_mipi_lvds2_sditf {
- status = "okay";
- port {
- mipi_lvds2_sditf: endpoint {
- remote-endpoint = <&isp_vir2>;
- };
- };
- };
- &rkisp_vir0 {
- status = "okay";
- port {
- #address-cells = <1>;
- #size-cells = <0>;
- isp_vir0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&mipi_lvds_sditf>;
- };
- };
- };
- &rkisp_vir2 {
- status = "okay";
- port {
- #address-cells = <1>;
- #size-cells = <0>;
- isp_vir2: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&mipi_lvds2_sditf>;
- };
- };
- };
- &rkcif {
- status = "okay";
- };
- &rkcif_mmu {
- status = "okay";
- };
- &rkisp {
- status = "okay";
- };
- &rkisp_mmu {
- status = "okay";
- };
复制代码
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