vivado自带仿真总是失败-IP核之双端口RAM实验

九品学院

elaborate.log 描述
Vivado Simulator 2020.2
Copyright 1986-1999, 2001-2020 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2020.2/bin/unwrapped/win64.o/xelab.exe -wto 4934f3cd3c6d4108843949bbb7c95276 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L blk_mem_gen_v8_4_4 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_ip_2port_ram_behav xil_defaultlib.tb_ip_2port_ram xil_defaultlib.glbl -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
ERROR: [VRFC 10-2063] Module <ila_0> not found while processing module instance <u_ila_0> [E:/FPGA/code/ip_2port_ram/rtl/ip_2port_ram.v:78]
ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed.


vivado界面Messages 和Hierarchy Simulation Sources如下



操作按文档来的，文件都是直接拷过来的，还是进不了调试。