原子哥,你好
我用的工具是vivado2023.1, 选择了启明星的7010芯片, 按照vitis开发指南, 参照dma 回路实验, 在broad design中添加了zynq, dma, fifo, 然后按照指南的流程,进行了配置和连线,在生成bitstream的时候,
出现了[Project 1-68] No files found to match top module 'system_wrapper'
Resolution: Please verify your EDIF file is named after its top module. For instance, if the top module is called 'viterbi', name the file 'viterbi.edf'. File naming is case sensitive on Linux.