xc7k325t使用uart重复发送数据

shadow1989 · 发表于 2022-11-1 10:22:35

使用k7系列fpga做cmos图像采集存储至bram中再由uart串口发送回上位机，这里uart每次会重复发送数据，请问是哪里有问题呢，代码如下：

//*******************uart***********************
wire rx_data_done;
wire [7:0] rx_data;
parameter CLK_FRE = 200; //Mhz
localparam IDLE = 0;
localparam SEND = 1; //send
localparam WAIT = 2; //wait 1 second and send uart received data
localparam STOP = 3;
reg [7:0] tx_data;
reg [7:0] tx_str;
reg tx_data_valid;
wire tx_data_ready;
reg [7:0] tx_cnt;
wire rx_data_valid;
wire rx_data_ready;
reg [3:0] state;
reg [23:0] pixel_cnt;
reg [23:0] off_cnt;
wire uart_vaild;
wire end_cnt;
reg uart_cnt;
reg [31:0] cnt_1s;
reg flag_1s;
assign rx_data_done = rx_data_valid;
assign rx_data_ready = 1'b1; //always can receive data
assign end_cnt = (off_cnt < 1000)? 1'b1:1'b0;
assign uart_vaild = uart_en && uart_cnt && end_cnt && bram_read_en;
always@(posedge sys_clk or negedge sys_rst_n)
begin
if(sys_rst_n == 1'b0)
begin
uart_cnt <= 1'b0;
cnt_1s <= 32'd0;
end
else
begin
if(pixel_cnt < 2500)
begin
uart_cnt <= 1'b1;
flag_1s <= 1'b0;
end
else
begin
uart_cnt <= 1'b0;
cnt_1s <= cnt_1s + 32'd1;
if(cnt_1s == 32'd200000000)
begin
cnt_1s <= 32'd0;
flag_1s <= 1'b1;
end
end
end
end
always@(posedge sys_clk or negedge sys_rst_n)
begin
if(sys_rst_n == 1'b0)
begin
tx_data <= 8'd0;
state <= IDLE;
tx_data_valid <= 1'b0;
pixel_cnt <= 24'b0;
off_cnt <= 24'b0;
end
else
begin
if(flag_1s == 1'b1)
pixel_cnt <= 24'b0;
if (uart_vaild == 1'b1)
begin
state <= IDLE;
case(state)
IDLE:
state <= SEND;
SEND:
begin
tx_data <= data_read;
if(tx_data_valid && tx_data_ready) //last byte sent is complete
begin
tx_data_valid <= 1'b0;
state <= WAIT;
end
else if(~tx_data_valid)
begin
tx_data_valid <= 1'b1;
end
end
WAIT:
begin
state <= STOP;
end
STOP:
begin
pixel_cnt <= pixel_cnt + 24'd1;
addr_read <= addr_read + 24'd1;
off_cnt <= off_cnt + 24'd1;
if(addr_read == 24'd1036801)
// if(addr_read == 24'd629856)
begin
addr_read <= 24'd0;
end
end
default:
state <= IDLE;
endcase
end
end
end
uart_rx#
(
.CLK_FRE(CLK_FRE),
.BAUD_RATE(115200)
) uart_rx_inst
(
.clk (sys_clk ),
.rst_n (sys_rst_n ),
.rx_data (rx_data ),
.rx_data_valid (rx_data_valid ),
.rx_data_ready (rx_data_ready ),
.rx_pin (uart_rx )
);
uart_tx#
(
.CLK_FRE(CLK_FRE),
.BAUD_RATE(115200)
) uart_tx_inst
(
.clk (sys_clk ),
.rst_n (sys_rst_n ),
.tx_data (tx_data ),
.tx_data_valid (tx_data_valid ),
.tx_data_ready (tx_data_ready ),
.tx_pin (uart_tx )
);
//*******************uart***************************

复制代码

uart发送数据的代码

module uart_tx
#(
parameter CLK_FRE = 50, //clock frequency(Mhz)
parameter BAUD_RATE = 115200 //serial baud rate
)
(
input clk, //clock input
input rst_n, //asynchronous reset input, low active
input [7:0] tx_data, //data to send
input tx_data_valid, //data to be sent is valid
output reg tx_data_ready, //send ready
output tx_pin //serial data output
);
//calculates the clock cycle for baud rate
localparam CYCLE = CLK_FRE * 1000000 / BAUD_RATE;
//state machine code
localparam S_IDLE = 1;
localparam S_START = 2; //start bit
localparam S_SEND_BYTE = 3; //data bits
localparam S_STOP = 4; //stop bit
reg [2:0] state;
reg [2:0] next_state;
reg [15:0] cycle_cnt; //baud counter
reg [2:0] bit_cnt; //bit counter
reg [7:0] tx_data_latch; //latch data to send
reg tx_reg; //serial data output
assign tx_pin = tx_reg;
always@(posedge clk or negedge rst_n)
begin
if(rst_n == 1'b0)
state <= S_IDLE;
else
state <= next_state;
end
always@(*)
begin
case(state)
S_IDLE:
if(tx_data_valid == 1'b1)
next_state <= S_START;
else
next_state <= S_IDLE;
S_START:
if(cycle_cnt == CYCLE - 1)
next_state <= S_SEND_BYTE;
else
next_state <= S_START;
S_SEND_BYTE:
if(cycle_cnt == CYCLE - 1 && bit_cnt == 3'd7)
next_state <= S_STOP;
else
next_state <= S_SEND_BYTE;
S_STOP:
if(cycle_cnt == CYCLE - 1)
next_state <= S_IDLE;
else
next_state <= S_STOP;
default:
next_state <= S_IDLE;
endcase
end
always@(posedge clk or negedge rst_n)
begin
if(rst_n == 1'b0)
tx_data_ready <= 1'b0;
else if(state == S_IDLE)
if(tx_data_valid == 1'b1)
tx_data_ready <= 1'b0;
else
tx_data_ready <= 1'b1;
else if(state == S_STOP && cycle_cnt == CYCLE - 1)
tx_data_ready <= 1'b1;
end
always@(posedge clk or negedge rst_n)
begin
if(rst_n == 1'b0)
tx_data_latch <= 8'd0;
else if(state == S_IDLE && tx_data_valid == 1'b1)
tx_data_latch <= tx_data;
end
always@(posedge clk or negedge rst_n)
begin
if(rst_n == 1'b0)
bit_cnt <= 3'd0;
else if(state == S_SEND_BYTE)begin
if(cycle_cnt == CYCLE - 1)
bit_cnt <= bit_cnt + 3'd1;
else
bit_cnt <= bit_cnt;
end
else
bit_cnt <= 3'd0;
end
always@(posedge clk or negedge rst_n)
begin
if(rst_n == 1'b0)
cycle_cnt <= 16'd0;
else if((state == S_SEND_BYTE && cycle_cnt == CYCLE - 1) || next_state != state)
cycle_cnt <= 16'd0;
else
cycle_cnt <= cycle_cnt + 16'd1;
end
always@(posedge clk or negedge rst_n)
begin
if(rst_n == 1'b0)
tx_reg <= 1'b1;
else
case(state)
S_IDLE,S_STOP:
tx_reg <= 1'b1;
S_START:
tx_reg <= 1'b0;
S_SEND_BYTE:
tx_reg <= tx_data_latch[bit_cnt];
default:
tx_reg <= 1'b1;
endcase
end
endmodule