请教一下同时开启定时器的问题

车嘉炜 · 发表于 2021-4-16 21:15:02

请问有没有可能让多个定时器在时间上严格的同时开启？比如说我想配置TIM1、2、3都输出pwm波，我希望他们波形在时域上是完全重合的，不要定时器逐个开启（这样输出的pwm波形彼此之间就会有时延），这该怎么实现呢？

xkwy · 发表于 2021-4-16 21:15:03

用定时器的主从模式啊，STM32那么强大的定时器，定时器间同步简直小菜一碟。

首先选择一个主定时器，如TIM1，将它的TRGO信号设定为001:Enable，即TIM1的EN位开启时输出1，关闭时输出0，需要操作的寄存器是TIMx_CR2，Bits 6:4 MMS[2:0]: Master mode selection
001: Enable - the Counter enable signal, CNT_EN, is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic OR between CEN control bit
and the trigger input when configured in gated mode.
When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register).

将其他从定时器的主触发源选择为IT1/IT2/IT3/IT4内部触发，即接收刚才的主定时器TIM1输出的TRGO信号，具体选择哪个内部触发源有一个表（ TIMx Internal trigger connection），查表得知，TIM2/TIM3/TIM4想接收TIM1的信号，对应要设置触发源为IT1。
需要操作的寄存器是TIMx_SMCR Bits 6:4 TS: Trigger selection

从定时器接收到了同步信号，接下来就是动作了，按照你的需求，此处应该设置为Gate模式，即主定时器开咱也开，主定时器停咱也停。
需要操作的寄存器是TIMx_SMCR Bits 2:0 SMS: Slave mode selection
101: Gated mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled

最后需要注意的是，要设置从定时器的Master/Slave mode，不然还是会有略微几个时钟的延迟。
需要操作的寄存器是TIMx_SMCR Bit 7 MSM: Master/Slave mode
1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.

这样之后就完美同步了，使用方法是先把所有从定时器EN都打开，
然后主定时器一开全部都开了，主定时器一关全部都关，只需要操作主定时器都EN就可