FPGA报错 大神们来看一下！！！！！！

fdsfgsgsdf

定义了一个15位的寄存器，如图是我定义的寄存器，结果编译报错，啥意思呀
Error (10170): Verilog HDL syntax error at hyperram_rw.v(14) near text: "reg";  expecting a direction. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/s ... ge-base/search.html and search for this specific error message number.

QinQZ

Verilog要以英文分号结尾，而不是逗号。还有这个寄存器是定义的16位，不是15位哦，大兄弟

playboy840325

兄弟  要用；不是，