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发表于 2020-4-29 11:52:25
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Info: Running Quartus II 64-Bit Analysis & Synthesis
Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Info: Processing started: Wed Apr 29 10:36:35 2020
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off 1 -c 1
Info (11104): Parallel Compilation has detected 4 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 2 of the 2 physical processors detected instead.
Info (12021): Found 1 design units, including 1 entities, in source file pic_rom1.v
Info (12023): Found entity 1: pic_rom1
Info (12021): Found 1 design units, including 1 entities, in source file pic_rom2.v
Info (12023): Found entity 1: pic_rom2
Info (12021): Found 1 design units, including 1 entities, in source file vga_display2.v
Info (12023): Found entity 1: vga_display2
Info (12021): Found 1 design units, including 1 entities, in source file vga_display1.v
Info (12023): Found entity 1: vga_display1
Info (12021): Found 1 design units, including 1 entities, in source file vga_driver.v
Info (12023): Found entity 1: vga_driver
Info (12021): Found 1 design units, including 1 entities, in source file choose.v
Info (12023): Found entity 1: choose
Info (12021): Found 1 design units, including 1 entities, in source file vga_pll.v
Info (12023): Found entity 1: vga_pll
Info (12021): Found 1 design units, including 1 entities, in source file vga_pic.bdf
Info (12023): Found entity 1: vga_pic
Info (12127): Elaborating entity "vga_pic" for the top level hierarchy
Info (12128): Elaborating entity "vga_driver" for hierarchy "vga_driver:inst3"
Info (12128): Elaborating entity "vga_pll" for hierarchy "vga_pll:inst"
Info (12128): Elaborating entity "altpll" for hierarchy "vga_pll:inst|altpll:altpll_component"
Info (12130): Elaborated megafunction instantiation "vga_pll:inst|altpll:altpll_component"
Info (12133): Instantiated megafunction "vga_pll:inst|altpll:altpll_component" with the following parameter:
Info (12134): Parameter "bandwidth_type" = "AUTO"
Info (12134): Parameter "clk0_divide_by" = "2"
Info (12134): Parameter "clk0_duty_cycle" = "50"
Info (12134): Parameter "clk0_multiply_by" = "1"
Info (12134): Parameter "clk0_phase_shift" = "0"
Info (12134): Parameter "compensate_clock" = "CLK0"
Info (12134): Parameter "inclk0_input_frequency" = "20000"
Info (12134): Parameter "intended_device_family" = "Cyclone IV E"
Info (12134): Parameter "lpm_hint" = "CBX_MODULE_PREFIX=vga_pll"
Info (12134): Parameter "lpm_type" = "altpll"
Info (12134): Parameter "operation_mode" = "NORMAL"
Info (12134): Parameter "pll_type" = "AUTO"
Info (12134): Parameter "port_activeclock" = "PORT_UNUSED"
Info (12134): Parameter "port_areset" = "PORT_USED"
Info (12134): Parameter "port_clkbad0" = "PORT_UNUSED"
Info (12134): Parameter "port_clkbad1" = "PORT_UNUSED"
Info (12134): Parameter "port_clkloss" = "PORT_UNUSED"
Info (12134): Parameter "port_clkswitch" = "PORT_UNUSED"
Info (12134): Parameter "port_configupdate" = "PORT_UNUSED"
Info (12134): Parameter "port_fbin" = "PORT_UNUSED"
Info (12134): Parameter "port_inclk0" = "PORT_USED"
Info (12134): Parameter "port_inclk1" = "PORT_UNUSED"
Info (12134): Parameter "port_locked" = "PORT_USED"
Info (12134): Parameter "port_pfdena" = "PORT_UNUSED"
Info (12134): Parameter "port_phasecounterselect" = "PORT_UNUSED"
Info (12134): Parameter "port_phasedone" = "PORT_UNUSED"
Info (12134): Parameter "port_phasestep" = "PORT_UNUSED"
Info (12134): Parameter "port_phaseupdown" = "PORT_UNUSED"
Info (12134): Parameter "port_pllena" = "PORT_UNUSED"
Info (12134): Parameter "port_scanaclr" = "PORT_UNUSED"
Info (12134): Parameter "port_scanclk" = "PORT_UNUSED"
Info (12134): Parameter "port_scanclkena" = "PORT_UNUSED"
Info (12134): Parameter "port_scandata" = "PORT_UNUSED"
Info (12134): Parameter "port_scandataout" = "PORT_UNUSED"
Info (12134): Parameter "port_scandone" = "PORT_UNUSED"
Info (12134): Parameter "port_scanread" = "PORT_UNUSED"
Info (12134): Parameter "port_scanwrite" = "PORT_UNUSED"
Info (12134): Parameter "port_clk0" = "PORT_USED"
Info (12134): Parameter "port_clk1" = "PORT_UNUSED"
Info (12134): Parameter "port_clk2" = "PORT_UNUSED"
Info (12134): Parameter "port_clk3" = "PORT_UNUSED"
Info (12134): Parameter "port_clk4" = "PORT_UNUSED"
Info (12134): Parameter "port_clk5" = "PORT_UNUSED"
Info (12134): Parameter "port_clkena0" = "PORT_UNUSED"
Info (12134): Parameter "port_clkena1" = "PORT_UNUSED"
Info (12134): Parameter "port_clkena2" = "PORT_UNUSED"
Info (12134): Parameter "port_clkena3" = "PORT_UNUSED"
Info (12134): Parameter "port_clkena4" = "PORT_UNUSED"
Info (12134): Parameter "port_clkena5" = "PORT_UNUSED"
Info (12134): Parameter "port_extclk0" = "PORT_UNUSED"
Info (12134): Parameter "port_extclk1" = "PORT_UNUSED"
Info (12134): Parameter "port_extclk2" = "PORT_UNUSED"
Info (12134): Parameter "port_extclk3" = "PORT_UNUSED"
Info (12134): Parameter "self_reset_on_loss_lock" = "OFF"
Info (12134): Parameter "width_clock" = "5"
Info (12021): Found 1 design units, including 1 entities, in source file db/vga_pll_altpll.v
Info (12023): Found entity 1: vga_pll_altpll
Info (12128): Elaborating entity "vga_pll_altpll" for hierarchy "vga_pll:inst|altpll:altpll_component|vga_pll_altpll:auto_generated"
Info (12128): Elaborating entity "7408" for hierarchy "7408:inst5"
Info (12130): Elaborated megafunction instantiation "7408:inst5"
Info (12128): Elaborating entity "choose" for hierarchy "choose:inst4"
Warning (10235): Verilog HDL Always Construct warning at choose.v(11): variable "picture1" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at choose.v(13): variable "picture2" is read inside the Always Construct but isn't in the Always Construct's Event Control
Info (12128): Elaborating entity "vga_display1" for hierarchy "vga_display1:inst1"
Info (12128): Elaborating entity "pic_rom1" for hierarchy "vga_display1:inst1|pic_rom1:pic_rom_inst"
Info (12128): Elaborating entity "altsyncram" for hierarchy "vga_display1:inst1|pic_rom1:pic_rom_inst|altsyncram:altsyncram_component"
Info (12130): Elaborated megafunction instantiation "vga_display1:inst1|pic_rom1:pic_rom_inst|altsyncram:altsyncram_component"
Info (12133): Instantiated megafunction "vga_display1:inst1|pic_rom1:pic_rom_inst|altsyncram:altsyncram_component" with the following parameter:
Info (12134): Parameter "address_aclr_a" = "NONE"
Info (12134): Parameter "clock_enable_input_a" = "BYPASS"
Info (12134): Parameter "clock_enable_output_a" = "BYPASS"
Info (12134): Parameter "init_file" = "./tupian/2.1.mif"
Info (12134): Parameter "intended_device_family" = "Cyclone IV E"
Info (12134): Parameter "lpm_hint" = "ENABLE_RUNTIME_MOD=NO"
Info (12134): Parameter "lpm_type" = "altsyncram"
Info (12134): Parameter "numwords_a" = "16384"
Info (12134): Parameter "operation_mode" = "ROM"
Info (12134): Parameter "outdata_aclr_a" = "NONE"
Info (12134): Parameter "outdata_reg_a" = "UNREGISTERED"
Info (12134): Parameter "widthad_a" = "14"
Info (12134): Parameter "width_a" = "16"
Info (12134): Parameter "width_byteena_a" = "1"
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_h2b1.tdf
Info (12023): Found entity 1: altsyncram_h2b1
Info (12128): Elaborating entity "altsyncram_h2b1" for hierarchy "vga_display1:inst1|pic_rom1:pic_rom_inst|altsyncram:altsyncram_component|altsyncram_h2b1:auto_generated"
Info (12021): Found 1 design units, including 1 entities, in source file db/decode_jsa.tdf
Info (12023): Found entity 1: decode_jsa
Info (12128): Elaborating entity "decode_jsa" for hierarchy "vga_display1:inst1|pic_rom1:pic_rom_inst|altsyncram:altsyncram_component|altsyncram_h2b1:auto_generated|decode_jsa:rden_decode"
Info (12021): Found 1 design units, including 1 entities, in source file db/mux_iob.tdf
Info (12023): Found entity 1: mux_iob
Info (12128): Elaborating entity "mux_iob" for hierarchy "vga_display1:inst1|pic_rom1:pic_rom_inst|altsyncram:altsyncram_component|altsyncram_h2b1:auto_generated|mux_iob:mux2"
Info (12128): Elaborating entity "vga_display2" for hierarchy "vga_display2:inst2"
Info (12128): Elaborating entity "pic_rom2" for hierarchy "vga_display2:inst2|pic_rom2:pic_rom_inst"
Info (12128): Elaborating entity "altsyncram" for hierarchy "vga_display2:inst2|pic_rom2:pic_rom_inst|altsyncram:altsyncram_component"
Info (12130): Elaborated megafunction instantiation "vga_display2:inst2|pic_rom2:pic_rom_inst|altsyncram:altsyncram_component"
Info (12133): Instantiated megafunction "vga_display2:inst2|pic_rom2:pic_rom_inst|altsyncram:altsyncram_component" with the following parameter:
Info (12134): Parameter "address_aclr_a" = "NONE"
Info (12134): Parameter "clock_enable_input_a" = "BYPASS"
Info (12134): Parameter "clock_enable_output_a" = "BYPASS"
Info (12134): Parameter "init_file" = "./tupian/2.2.mif"
Info (12134): Parameter "intended_device_family" = "Cyclone IV E"
Info (12134): Parameter "lpm_hint" = "ENABLE_RUNTIME_MOD=NO"
Info (12134): Parameter "lpm_type" = "altsyncram"
Info (12134): Parameter "numwords_a" = "16384"
Info (12134): Parameter "operation_mode" = "ROM"
Info (12134): Parameter "outdata_aclr_a" = "NONE"
Info (12134): Parameter "outdata_reg_a" = "UNREGISTERED"
Info (12134): Parameter "widthad_a" = "14"
Info (12134): Parameter "width_a" = "16"
Info (12134): Parameter "width_byteena_a" = "1"
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_i2b1.tdf
Info (12023): Found entity 1: altsyncram_i2b1
Info (12128): Elaborating entity "altsyncram_i2b1" for hierarchy "vga_display2:inst2|pic_rom2:pic_rom_inst|altsyncram:altsyncram_component|altsyncram_i2b1:auto_generated"
Info (286030): Timing-Driven Synthesis is running
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
Info (16011): Adding 1 node(s), including 0 DDIO, 1 PLL, 0 transceiver and 0 LCELL
Info (21057): Implemented 232 device resources after synthesis - the final resource count might be different
Info (21058): Implemented 4 input pins
Info (21059): Implemented 18 output pins
Info (21061): Implemented 145 logic cells
Info (21064): Implemented 64 RAM segments
Info (21065): Implemented 1 PLLs
Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 2 warnings
Info: Peak virtual memory: 4665 megabytes
Info: Processing ended: Wed Apr 29 10:36:57 2020
Info: Elapsed time: 00:00:22
Info: Total CPU time (on all processors): 00:00:03
Info (11104): Parallel Compilation has detected 4 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 2 of the 2 physical processors detected instead.
Info (119006): Selected device EP4CE10F17C8 for design "1"
Info (21077): Core supply voltage is 1.2V
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Info (15535): Implemented PLL "vga_pll:inst|altpll:altpll_component|vga_pll_altpll:auto_generated|pll1" as Cyclone IV E PLL type
Info (15099): Implementing clock multiplication of 1, clock division of 2, and phase shift of 0 degrees (0 ps) for vga_pll:inst|altpll:altpll_component|vga_pll_altpll:auto_generated|wire_pll1_clk[0] port
Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
Info (176445): Device EP4CE6F17C8 is compatible
Info (176445): Device EP4CE15F17C8 is compatible
Info (176445): Device EP4CE22F17C8 is compatible
Info (169124): Fitter converted 5 user pins into dedicated programming pins
Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location C1
Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location D2
Info (169125): Pin ~ALTERA_DCLK~ is reserved at location H1
Info (169125): Pin ~ALTERA_DATA0~ is reserved at location H2
Info (169125): Pin ~ALTERA_nCEO~ is reserved at location F16
Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
Critical Warning (169085): No exact pin location assignment(s) for 22 pins of 22 total pins
Info (169086): Pin vga_hs not assigned to an exact location on the device
Info (169086): Pin vga_vs not assigned to an exact location on the device
Info (169086): Pin vga_rgb[15] not assigned to an exact location on the device
Info (169086): Pin vga_rgb[14] not assigned to an exact location on the device
Info (169086): Pin vga_rgb[13] not assigned to an exact location on the device
Info (169086): Pin vga_rgb[12] not assigned to an exact location on the device
Info (169086): Pin vga_rgb[11] not assigned to an exact location on the device
Info (169086): Pin vga_rgb[10] not assigned to an exact location on the device
Info (169086): Pin vga_rgb[9] not assigned to an exact location on the device
Info (169086): Pin vga_rgb[8] not assigned to an exact location on the device
Info (169086): Pin vga_rgb[7] not assigned to an exact location on the device
Info (169086): Pin vga_rgb[6] not assigned to an exact location on the device
Info (169086): Pin vga_rgb[5] not assigned to an exact location on the device
Info (169086): Pin vga_rgb[4] not assigned to an exact location on the device
Info (169086): Pin vga_rgb[3] not assigned to an exact location on the device
Info (169086): Pin vga_rgb[2] not assigned to an exact location on the device
Info (169086): Pin vga_rgb[1] not assigned to an exact location on the device
Info (169086): Pin vga_rgb[0] not assigned to an exact location on the device
Info (169086): Pin xuanzw[0] not assigned to an exact location on the device
Info (169086): Pin xuanzw[1] not assigned to an exact location on the device
Info (169086): Pin sys_rst_n not assigned to an exact location on the device
Info (169086): Pin sys_clk not assigned to an exact location on the device
Critical Warning (332012): Synopsys Design Constraints File file not found: '1.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Info (332144): No user constrained generated clocks found in the design
Info (332144): No user constrained base clocks found in the design
Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
Info (176353): Automatically promoted node vga_pll:inst|altpll:altpll_component|vga_pll_altpll:auto_generated|wire_pll1_clk[0] (placed in counter C0 of PLL_1)
Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3
Info (176353): Automatically promoted node sys_rst_n~input (placed in PIN M2 (CLK2, DIFFCLK_1p))
Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4
Info (176356): Following destination nodes may be non-global or may not use global or regional clocks
Info (176357): Destination node 7408:inst5|4~0
Info (176353): Automatically promoted node 7408:inst5|4~0
Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
Info (176233): Starting register packing
Info (176235): Finished register packing
Extra Info (176219): No registers were packed into other blocks
Info (176214): Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
Info (176211): Number of I/O pins in group: 20 (unused VREF, 2.5V VCCIO, 2 input, 18 output, 0 bidirectional)
Info (176212): I/O standards used: 2.5 V.
Info (176215): I/O bank details before I/O pin placement
Info (176214): Statistics of I/O banks
Info (176213): I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 5 total pin(s) used -- 12 pins available
Info (176213): I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 18 pins available
Info (176213): I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 26 pins available
Info (176213): I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 27 pins available
Info (176213): I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 25 pins available
Info (176213): I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 13 pins available
Info (176213): I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 26 pins available
Info (176213): I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 26 pins available
Info (171121): Fitter preparation operations ending: elapsed time is 00:00:05
Info (170189): Fitter placement preparation operations beginning
Error (170040): Can't place all RAM cells in design
Info (170034): Selected device has 46 memory locations of type M9K. The current design requires 64 memory locations of type M9K to successfully fit.
Info (170033): Memory usage required for the design in the current device: 139% M9K memory block locations required
Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
Info (11888): Total time spent on timing analysis during the Fitter is 0.02 seconds.
Error (171000): Can't fit design in device
Info (144001): Generated suppressed messages file E:/QuartusCode/TupianYuanlitu/output_files/1.fit.smsg
Error: Quartus II 64-Bit Fitter was unsuccessful. 2 errors, 3 warnings
Error: Peak virtual memory: 5048 megabytes
Error: Processing ended: Wed Apr 29 10:37:17 2020
Error: Elapsed time: 00:00:17
Error: Total CPU time (on all processors): 00:00:05
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发表于 2020-4-27 19:01:22
发表于 2020-4-28 01:25:00
，编辑模式改成高级模式，可以贴图片
