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我的数字电子时钟的小时计时与校时模块出现以下错误，哪位大虾解救一下！！
//DATA_H 初始化时钟小时数据，6’b000000
//HOUR 小时数据输出
//CLK 分钟进位信号
//D1,D2 小时校时加，减使能信号
//KEN1,KEN2 小时校时加，减模块的复位或计时选择信号
//TS 计时，秒校时，分校时，时校时四种状态选择
module hou_change(DATA_H,HOUR,CLK,D1,D2,KEN1,KEN2,TS);
output [4:0]HOUR;
input [4:0]DATA_H;
input CLK;
input D1;
input D2;
input [1:0]TS;
input KEN1;
input KEN2;
reg [4:0]HOUR;
reg CLK1;
reg CLK2;
always @(TS)
begin
if(TS==2'b11)
CLK1=D1;
else
CLK1=CLK;
end
always @(TS)
begin
if(TS==2'b11)
CLK2=D2;
else
CLK2=CLK;
end
always @(posedge CLK1 or negedge KEN1 or posedge CLK2 or negedge KEN2)
begin
if(!KEN1)
begin
HOUR<=DATA_H;
end
else
begin
if(TS==2'b00) //双击错误一，光标跳转处
begin
if(HOUR<=5'b10110 )
begin
HOUR<=HOUR+1'b1;
end
else
begin
HOUR<=5'b00000;
end
end
else if(TS==2'b11)
begin
if(HOUR<=5'b10110)
begin
HOUR<=HOUR+1'b1;
end
else
begin
HOUR<=5'b00000;
end
end
else
begin
HOUR<=HOUR;
end
end
if(!KEN2)
begin
HOUR<=DATA_H;
end
else
begin
if(TS==2'b00) //双击错误二，光标跳转处
begin
if(HOUR<=5'b10110 )
begin
HOUR<=HOUR+1'b1;
end
else
begin
HOUR<=5'b00000;
end
end
else if(TS==2'b11)
begin
if(HOUR>5'b00000&&HOUR<=5'b10111)
begin
HOUR<=HOUR-1'b1;
end
else
begin
HOUR<=5'b10111;
end
end
else
begin
HOUR<=HOUR;
end
end
end
endmodule
Error (10200): Verilog HDL Conditional Statement error at hou_change.v(55): cannot match operand(s) in the condition to the corresponding edges in the enclosing event control of the always construct
Error (10200): Verilog HDL Conditional Statement error at hou_change.v(89): cannot match operand(s) in the condition to the corresponding edges in the enclosing event control of the always construct
Error (12153): Can't elaborate top-level user hierarchy
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发表于 2014-4-12 15:22:05
发表于 2014-4-12 20:18:49
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