FPGA编译后很多警告咋回事？别人编译没问题

qzxht1988

如题，我按照例程编译了程序，有很多
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.

Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.

Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details

Critical Warning (332012): Synopsys Design Constraints File file not found: 'KEY_LED.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.

Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.

Critical Warning (332148): Timing requirements not met
        Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.

932904676xy

一般来说警告是不用管的，但严重警告是必须要处理的，不处理的话会影响功能的

qzxht1988

不要沉下去了啊！

MY40130064

第一二个据说是影响编译时速度，有个设置可以设置编译时指定电脑几个核工作之类的吧  
第三个是有些IO使用的默认值，比如说默认值 2.5V TTL 打开PIN表可以看到
第四个是没有找到时序约束文件，入门一般就是PLL的时序约束，可自动生成。
第六个时序不满足要求，

第四六个有点问题，解决四应该六就会没了  不管运行应该是没问题的。

Laughing11

我也出现了，就没人能解答下么

15229283912

时序约束没有？