新手入门
- 积分
- 10
- 金钱
- 10
- 注册时间
- 2019-5-12
- 在线时间
- 2 小时
|
楼主 |
发表于 2019-7-3 22:55:35
|
显示全部楼层
本帖最后由 snakeqx 于 2019-7-3 22:58 编辑
我好像明白了. 根据视频介绍:
因为<=的赋值是并发的,而且整个一个always里面都是并发的,所以先全部算右值,再赋值左边.
于是我"错过"了切换的机会, 而下次触发的时候1已经移出范围,导致LED里的值全是0,而且因为没有1了,后面怎么移也不会有1.
我改了一下代码,至少运行正常了.
还请各位能指点一下是不是这样的.
- module verilog_test (
- input clk,
- input rst_n,
- output reg[3:0] led
- );
- // to set up a counter for every 0.2 s
- // 1 second / 50MHz = 0.2 / xHz =? x = 10MHz
- // to hold 10_000_000, it needs 24 bit.
- reg [23:0] counter;
- reg [1:0] led_status; //to judge the led status
- reg direction_flag; //dicide which direction the led flow
- parameter CNT_200MS = 24'd10_000_000 -1'b1;
- //generate signal with 10MHz (0.2s)
- always @ (posedge clk or negedge rst_n) begin
- if(!rst_n)
- counter <= 24'd0;
- else begin
- if(counter < CNT_200MS)
- counter <= counter + 1'b1;
- else
- counter <= 24'd0;
- end
-
- end
- // +/- flow_led
- always @ (posedge clk or negedge rst_n) begin
- if(!rst_n) begin
- // initialize
- led_status <= 2'b01; //////////////////////这里从1开始
- direction_flag <= 1'b1;
- led <= 4'b0001;
- end
- // every 200ms trigger
- else if (counter == CNT_200MS) begin
- // status + 1
- led_status <= led_status + 1'b1;
- // judge status to decide direction
- if (led_status == 2'b11) begin
- direction_flag <= ~direction_flag;
- led_status <= 2'b01; /////////////////////////只用3位,所以这里回复1
- end
- else
- direction_flag <= direction_flag;
- // flow according direction
- if (direction_flag)
- led = led << 1;
- else
- led = led >> 1;
- end
- else
- led <= led;
- end
- endmodule
复制代码
|
|