关于pwm的问题

七七九八

/* TIM1 Configuration --------------------------------------------------- 00069    Generate 7 PWM signals with 4 different duty cycles: 00070    TIM1CLK = SystemCoreClock, Prescaler = 0, TIM1 counter clock = SystemCoreClock 00071    SystemCoreClock is set to 72 MHz for Low-density, Medium-density, High-density 00072    and Connectivity line devices and to 24 MHz for Low-Density Value line and 00073    Medium-Density Value line devices 00074     00075    The objective is to generate 7 PWM signal at 17.57 KHz: 00076      - TIM1_Period = (SystemCoreClock / 17570) - 1 00077    The channel 1 and channel 1N duty cycle is set to 50% 00078    The channel 2 and channel 2N duty cycle is set to 37.5% 00079    The channel 3 and channel 3N duty cycle is set to 25% 00080    The channel 4 duty cycle is set to 12.5% 00081    The Timer pulse is calculated as follows: 00082      - ChannelxPulse = DutyCycle * (TIM1_Period - 1) / 100 00083   ----------------------------------------------------------------------- */ 00084   /* Compute the value to be set in ARR regiter to generate signal frequency at 17.57 Khz */ 00085   TimerPeriod = (SystemCoreClock / 17570 ) - 1;00086   /* Compute CCR1 value to generate a duty cycle at 50% for channel 1 and 1N */ 00087   Channel1Pulse = (uint16_t) (((uint32_t) 5 * (TimerPeriod - 1)) / 10);00088   /* Compute CCR2 value to generate a duty cycle at 37.5%  for channel 2 and 2N */ 00089   Channel2Pulse = (uint16_t) (((uint32_t) 375 * (TimerPeriod - 1)) / 1000);00090   /* Compute CCR3 value to generate a duty cycle at 25%  for channel 3 and 3N */ 00091   Channel3Pulse = (uint16_t) (((uint32_t) 25 * (TimerPeriod - 1)) / 100);00092   /* Compute CCR4 value to generate a duty cycle at 12.5%  for channel 4 */ 00093   Channel4Pulse = (uint16_t) (((uint32_t) 125 * (TimerPeriod- 1)) / 1000);

怎么算的占空比？不是 = pulse/(period+1)吗？还有频率？[/mw_shl_code]

七七九八

/* TIM1 Configuration ---------------------------------------------------
00069    Generate 7 WM signals with 4 different duty cycles:
00070    TIM1CLK = SystemCoreClock, rescaler = 0, TIM1 counter clock = SystemCoreClock
00071    SystemCoreClock is set to 72 MHz for Low-density, Medium-density, High-density
00072    and Connectivity line devices and to 24 MHz for Low-Density Value line and
00073    Medium-Density Value line devices
00074    
00075    The objective is to generate 7 WM signal at 17.57 KHz:
00076      - TIM1_Period = (SystemCoreClock / 17570) - 1
00077    The channel 1 and channel 1N duty cycle is set to 50%
00078    The channel 2 and channel 2N duty cycle is set to 37.5%
00079    The channel 3 and channel 3N duty cycle is set to 25%
00080    The channel 4 duty cycle is set to 12.5%
00081    The Timer pulse is calculated as follows:
00082      - ChannelxPulse = DutyCycle * (TIM1_Period - 1) / 100
00083   ----------------------------------------------------------------------- */
00084   /* Compute the value to be set in ARR regiter to generate signal frequency at 17.57 Khz */
00085   TimerPeriod = (SystemCoreClock / 17570 ) - 1;
00086   /* Compute CCR1 value to generate a duty cycle at 50% for channel 1 and 1N */
00087   Channel1Pulse = (uint16_t) (((uint32_t) 5 * (TimerPeriod - 1)) / 10);
00088   /* Compute CCR2 value to generate a duty cycle at 37.5%  for channel 2 and 2N */
00089   Channel2Pulse = (uint16_t) (((uint32_t) 375 * (TimerPeriod - 1)) / 1000);
00090   /* Compute CCR3 value to generate a duty cycle at 25%  for channel 3 and 3N */
00091   Channel3Pulse = (uint16_t) (((uint32_t) 25 * (TimerPeriod - 1)) / 100);
00092   /* Compute CCR4 value to generate a duty cycle at 12.5%  for channel 4 */
00093   Channel4Pulse = (uint16_t) (((uint32_t) 125 * (TimerPeriod- 1)) / 1000);

七七九八

回复【2楼】七七九八:
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上面是固件库上面的内容

正点原子

这个我们教程就讲了。
占空比其实就是CCRx和arr-CCRx的比值。