资深版主
- 积分
- 4306
- 金钱
- 4306
- 注册时间
- 2018-6-30
- 在线时间
- 808 小时
|
本帖最后由 1208 于 2018-10-24 12:56 编辑
TIM_ITConfig(TIM1,TIM_IT_Update | TIM_IT_CC3,ENABLE);
用到上面的函数TIM_UP对应DMA的通道5
用到了输出比较中断函数TIM1_CC_IRQHandler(void)
更新中断函数TIM1_UP_IRQHandler(void)
DMA用DMA_DIR_PeripheralDST从内存读取发送到外设
用到了外设地址TIM1_CCR3_Address;
[mw_shl_code=c,true]定时器
uint16_t SRC_Buffer[10] = {100, 200, 300,400,500,600,700,800,900,1000};
#define TIM1_CCR3_Address 0x40012C3C
//uint16_t SRC_Buffer[3]={0,0,0};
uint16_t TimerPeriod = 0;
void TIM2_Configuration(void)
{
TimerPeriod = 1000;
// /* Compute CCR1 value to generate a duty cycle at 50% */
// SRC_Buffer[0] = (uint16_t) (((uint32_t) 5 * (TimerPeriod - 1)) / 10);
// /* Compute CCR1 value to generate a duty cycle at 37.5% */
// SRC_Buffer[1] = (uint16_t) (((uint32_t) 375 * (TimerPeriod - 1)) / 1000);
// /* Compute CCR1 value to generate a duty cycle at 25% */
// SRC_Buffer[2] = (uint16_t) (((uint32_t) 25 * (TimerPeriod - 1)) / 100);
SRC_Buffer[0] = 100;
/* Compute CCR1 value to generate a duty cycle at 37.5% */
SRC_Buffer[1] = 200;
/* Compute CCR1 value to generate a duty cycle at 25% */
SRC_Buffer[2] = 300;
NVIC_InitTypeDef NVIC_InitStructure;
TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;
TIM_OCInitTypeDef TIM_OCInitStructure;
RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM1,ENABLE);
TIM_TimeBaseStructure.TIM_Prescaler = 7200-1;
TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
TIM_TimeBaseStructure.TIM_Period = TimerPeriod;
TIM_TimeBaseStructure.TIM_ClockDivision = 0;
TIM_TimeBaseStructure.TIM_RepetitionCounter = 0;
TIM_TimeBaseInit(TIM1, &TIM_TimeBaseStructure);
/* Channel 3 Configuration in PWM mode */
TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM2;
TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
TIM_OCInitStructure.TIM_OutputNState = TIM_OutputNState_Enable;
TIM_OCInitStructure.TIM_Pulse = SRC_Buffer[0];
TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_Low;
TIM_OCInitStructure.TIM_OCNPolarity = TIM_OCNPolarity_Low;
TIM_OCInitStructure.TIM_OCIdleState = TIM_OCIdleState_Set;
TIM_OCInitStructure.TIM_OCNIdleState = TIM_OCIdleState_Reset;
TIM_OC3Init(TIM1, &TIM_OCInitStructure);
/* TIM1 Update DMA Request enable */
TIM_DMACmd(TIM1, TIM_DMA_Update, ENABLE);
NVIC_InitStructure.NVIC_IRQChannel = TIM1_UP_IRQn;//串口1是DMA1_4通道 ADC
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;//强占0
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;//子1
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init(&NVIC_InitStructure);
NVIC_InitStructure.NVIC_IRQChannel = TIM1_CC_IRQn;//串口1是DMA1_4通道 ADC
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;//强占0
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;//子1
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init(&NVIC_InitStructure);
/* TIM1 counter enable */
TIM_ITConfig(TIM1,TIM_IT_Update | TIM_IT_CC3,ENABLE);
/* Main Output Enable */
TIM_Cmd(TIM1, ENABLE);
TIM_CtrlPWMOutputs(TIM1, ENABLE);
}
void TIM1_UP_IRQHandler(void)
{
if(TIM_GetITStatus(TIM1,TIM_IT_Update)==1)
{
TIM_ClearITPendingBit(TIM1,TIM_IT_Update);
printf("UPccr=%d\r\n", *((u32 *)TIM1_CCR3_Address) );
}
}
void TIM1_CC_IRQHandler(void)
{
if(TIM_GetITStatus(TIM1,TIM_IT_CC3)==1)
{
TIM_ClearITPendingBit(TIM1,TIM_IT_CC3);
printf("CCccr=%d\r\n", *((u32 *)TIM1_CCR3_Address) );
}
}
DMA的
void DMA_Configuration(void)
{
DMA_InitTypeDef DMA_InitStructure;
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE);
/* DMA1 Channel5 Config */
DMA_DeInit(DMA1_Channel5);
DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)TIM1_CCR3_Address;
DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)SRC_Buffer;
DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
DMA_InitStructure.DMA_BufferSize = 10;
DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;
DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
DMA_InitStructure.DMA_Mode = DMA_Mode_Circular;
DMA_InitStructure.DMA_Priority = DMA_Priority_High;
DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
DMA_Init(DMA1_Channel5, &DMA_InitStructure);
/* DMA1 Channel5 enable */
DMA_Cmd(DMA1_Channel5, ENABLE);
}[/mw_shl_code]
|
|