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发表于 2017-8-18 10:49:17
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本帖最后由 veis 于 2017-8-18 10:52 编辑
我的不知道为什么不行,
typedef struct
{
vu16 LCD_REG;
vu16 LCD_RAM;
} LCD_TypeDef;
//HADDR[27,26]=00 A16
// 1 1111 1111 1110=0x1FFFE
#define LCD_BASE ((u32)(0x60000000 | 0x0001FFFE))
RCC->AHB1ENR|=0XF<<3;
RCC->AHB1ENR|=1<<1;
RCC->AHB1ENR|=1<<0;
RCC->AHB3ENR|=1<<0;
GPIO_Set(GPIOB,PIN15,GPIO_MODE_OUT,GPIO_OTYPE_PP,GPIO_SPEED_50M,GPIO_PUPD_PU);
GPIO_Set(GPIOD,(3<<0)|(3<<4)|(7<<8)|(3<<14),GPIO_MODE_AF,GPIO_OTYPE_PP,GPIO_SPEED_100M,GPIO_PUPD_PU); //PD0,1,4,5,8,9,10,14,15 AF OUT
GPIO_Set(GPIOE,(0X1FF<<7),GPIO_MODE_AF,GPIO_OTYPE_PP,GPIO_SPEED_100M,GPIO_PUPD_PU); //PE7~15,AF OUT
GPIO_Set(GPIOD,PIN11,GPIO_MODE_AF,GPIO_OTYPE_PP,GPIO_SPEED_100M,GPIO_PUPD_PU); //PD11,FSMC_A16
GPIO_Set(GPIOD,PIN7,GPIO_MODE_AF,GPIO_OTYPE_PP,GPIO_SPEED_100M,GPIO_PUPD_PU); //PD7,FSMC_NE1 GPIO_AF_Set(GPIOD,0,12); //PD0,AF12
GPIO_AF_Set(GPIOD,1,12); //PD1,AF12
GPIO_AF_Set(GPIOD,4,12); //PD4,AF12
GPIO_AF_Set(GPIOD,5,12); //PD5,AF12
GPIO_AF_Set(GPIOD,8,12); //PD8,AF12
GPIO_AF_Set(GPIOD,9,12); //PD9,AF12
GPIO_AF_Set(GPIOD,10,12); //PD10,AF12
GPIO_AF_Set(GPIOD,14,12); //PD14,AF12
GPIO_AF_Set(GPIOD,15,12); //PD15,AF12
GPIO_AF_Set(GPIOD,7,12); //PD7,AF12
GPIO_AF_Set(GPIOD,11,12); //PD11,AF12
GPIO_AF_Set(GPIOE,7,12); //PE7,AF12
GPIO_AF_Set(GPIOE,8,12); //PE8,AF12
GPIO_AF_Set(GPIOE,9,12); //PE9,AF12
GPIO_AF_Set(GPIOE,10,12); //PE10,AF12
GPIO_AF_Set(GPIOE,11,12); //PE11,AF12
GPIO_AF_Set(GPIOE,12,12); //PE12,AF12
GPIO_AF_Set(GPIOE,13,12); //PE13,AF12
GPIO_AF_Set(GPIOE,14,12); //PE14,AF12
GPIO_AF_Set(GPIOE,15,12); //PE15,AF12
FSMC_Bank1->BTCR[0]=0X00000000;
FSMC_Bank1->BTCR[1]=0X00000000;
FSMC_Bank1E->BWTR[0]=0X00000000;
FSMC_Bank1->BTCR[0]|=1<<12;
FSMC_Bank1->BTCR[0]|=1<<14;
FSMC_Bank1->BTCR[0]|=1<<4;
FSMC_Bank1->BTCR[1]|=0<<28;
FSMC_Bank1->BTCR[1]|=0XF<<0; //HCLK 1/168M=6ns*15=90ns
FSMC_Bank1->BTCR[1]|=60<<8; //HCLK=6*60=360ns
FSMC_Bank1E->BWTR[0]|=0<<28;
FSMC_Bank1E->BWTR[0]|=9<<0; //HCLK=54ns
FSMC_Bank1E->BWTR[0]|=8<<8; //HCLK=54ns
FSMC_Bank1->BTCR[0]|=1<<0; //使能BANK1,区域1
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