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发表于 2017-10-16 19:14:26
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本帖最后由 天空淡云 于 2017-10-20 14:51 编辑
在网上找到相关的寄存器配置,有需要的朋友可以参考一下 *** ADC INITIALIZATION ***
TIM1->ARRH= (u8)(AUTORELOAD >> 8); // set autoreload register for trigger period
TIM1->ARRL= (u8)(AUTORELOAD); //
TIM1->CCR1H= (u8)((AUTORELOAD-AD_STAB) >> 8); // set compare register for trigger period
TIM1->CCR1L= (u8)(AUTORELOAD-AD_STAB);
TIM1->CR1|= TIM1_CR1_ARPE; // auto reload register is buferred
TIM1->CR2= (4<<4) & TIM1_CR2_MMS; // CC1REF is used as TRGO
TIM1->CCMR1= (6<<4) & TIM1_CCMR_OCM; // CC1REF in PWM 1 mode
TIM1->IER|= TIM1_IER_CC1IE; // CC1 interrupt enable
TIM1->CCER1|= TIM1_CCER1_CC1P; // CC1 negative polarity
TIM1->CCER1|= TIM1_CCER1_CC1E; // CC1 output enable
TIM1->BKR|= TIM1_BKR_MOE;
TIM1->SMCR|= TIM1_SMCR_MSM; // synchronization of TRGO with ADC
TIM1->CR1|= TIM1_CR1_CEN; // timer 1 enable
ADC1->CSR= ADC1_CSR_EOCIE | (9 & ADC1_CSR_CH); // ADC EOC interrupt enable, channel 9
ADC1->CR1= 4<<4 & ADC1_CR1_SPSEL; // master clock/8, single conversion
ADC1->CR2= ADC1_CR2_EXTTRIG; // external trigger on timer 1 TRGO, left alignment
ADC1->TDRH= 2; // disable Schmitt trigger on AD input 9
ADC1->TDRL= 0; //
// init ADC variables
AD_samp= 0; // number of stored samples 0
ADInit= TRUE; // ADC initialized
ADSampRdy= FALSE; // No sample
ADC1->CR1|= ADC1_CR1_ADON; // ADC on
enableInterrupts(); // enable all interrupts [/mw_shl_code]
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