stm32f103zet6 外接8位并口EEPROM无法读写

qinfeng2002 · 发表于 2015-4-10 21:01:52

原子哥：
我用的EEPROM是AT28LV010，我把资料上传了，见附件，资料上说AT28LV010可以像SRAM一样进行访问，我用示波器看了一下,NWE,NE3，A0，D0的状态，发现NWE 写一次，会有两次变成低电平，数据传输太快，地址还未建立，数据已经有效了，我将BCR寄存器设置为SRAM已经8位宽度了，可是为什么NWE会变低两次呢？
请看我的原理图和源码：

#define Bank1_SRAM3_ADDR    ((u32)(0x68000000))

//初始化SRAM
void FSMC_SRAM_Init(void)
{
RCC->AHBENR |=(1<<8)|(1<<2); //使能FSMC时钟
RCC->APB2ENR|=(1<<5);        //端口D使能
RCC->APB2ENR|=(1<<6);        //端口E使能
  RCC->APB2ENR|=(1<<7);        //端口F使能
RCC->APB2ENR|=(1<<8);        //端口G使能

//RCC->APB2ENR|=1<0; //复用功能使能

//PORTD复用功能配置
/* PD.00(D2), PD.01(D3), PD.04(NOE), PD.05(NWE) PD.07(NE)*/
GPIOD->CRL&=0X0F00FF00;
GPIOD->CRL|=0XB0BB00BB;
/* PD.11(A16), PD.14(D0), PD.15(D1) */
GPIOD->CRH&=0X00FF0FFF;
GPIOD->CRH|=0XBB00B000;
//PORTE复用功能配置
/* PE.07(D4) */
GPIOE->CRL&=0X0FFFFFFF;
GPIOE->CRL|=0XB0000000;
/* PE.08(D5), PE.09(D6), PE.10(D7) */
GPIOE->CRH&=0XFFFFF000;
GPIOE->CRH|=0X00000BBB;

//PORTF复用功能配置
/* PF.00(A0), PF.01(A1), PF.02(A2), PF.03(A3), PF.04(A4), PF.05(A5) */
GPIOF->CRL&=0XFF000000;
GPIOF->CRL|=0X00BBBBBB;
/* PF.12(A6), PF.13(A7), PF.14(A8), PF.15(A9) */
GPIOF->CRH&=0X0000FFFF;
GPIOF->CRH|=0XBBBB0000;

//PORTG复用功能配置
/* PG.00(A10), PG.01(A11), PG.02(A12), PG.03(A13), PG.04(A14), PG.05(A15) */
  GPIOG->CRL&=0XFF000000;
GPIOG->CRL|=0X00BBBBBB;
//PG10 NE3
GPIOG->CRH&=0XFFFFF0FF;
GPIOG->CRH|=0X00000B00;

//时序配置
FSMC_Bank1->BCR3=0X00000000;
FSMC_Bank1->BTR3=0X00000000;
FSMC_Bank1E->BWTR[2]=0X00000000;
  FSMC_Bank1->BCR3&=(~(1<<19));//
FSMC_Bank1->BCR3|=((1<<14));//扩展模式禁止

FSMC_Bank1->BCR3&=(~(1<<13));//禁用WAIT信号

FSMC_Bank1->BCR3|=(1<<12);//存储器写使能
FSMC_Bank1->BCR3&=(~(3<<4)); //宽度为8位
FSMC_Bank1->BCR3&=(~(3<<2)); //存储器为sram
FSMC_Bank1->BCR3&=(~(1<<1)); //不复用数据地址总线
FSMC_Bank1->BCR3|=(1<<0); //使能存储快
//时序配置
    FSMC_Bank1->BTR3&=(~(15<<28));
//都采用最大值
FSMC_Bank1->BTR3|=(255<<8);
FSMC_Bank1->BTR3|=(15<<4);
FSMC_Bank1->BTR3|=(15<<0);

FSMC_Bank1E->BWTR[2]=0x0FFFFFFF;
}
void FSMC_SRAM_WriteBuffer(u8* pBuffer,u32 WriteAddr,u32 n)
{
u32 i;

for(i=0;i<n;i++)
{
  *((vu8*)(Bank1_SRAM3_ADDR+WriteAddr+i))=pBuffer;
}
delay_ms(12);
}
void FSMC_SRAM_ReadBuffer(u8* pBuffer,u32 ReadAddr,u32 n)
{
u32 i;
for(i=0;i<n;i++)
{
  pBuffer=*((vu8*)(Bank1_SRAM3_ADDR+ReadAddr+i));
}
}