[mw_shl_code=c,true]PWM控制模块代码[/mw_shl_code]
[mw_shl_code=c,true]
[mw_shl_code=c,true]/********************************************************************
* Module Name :
* Engineer : open
* Target Device : EP4CE6F17C8
* Tool versions : Quartus II 12.0
* Create Date : 2015-4-1
* Revision : v1.0
* Description :
/**********************************************************************/
module pwm_control(
clk,
rst_n,
pwm_out
);
/**********************************************************************/
parameter T_10K = 4999;
input clk ;
input rst_n ;
output pwm_out ;
reg pwm_out ;
reg [12:0] pwm_with;
/**********************************************************************/
reg [12:0] pwm_count;
always@ (posedge clk or negedge rst_n)begin
if(!rst_n)begin
pwm_count <= 0;
end
else if(pwm_count == T_10K)begin
pwm_count <= 0;
end
else begin
pwm_count <= pwm_count + 1'b1;
end
end
/************************************************************/
reg flag;
always@ (posedge clk or negedge rst_n)begin
if(!rst_n)begin
pwm_with <= 0;
flag <= 1;
end
else if(pwm_count == T_10K)begin
if(flag == 1)begin
if(pwm_with == 0)begin
flag <= 0;
end
else begin
pwm_with <= pwm_with - 1'b1;
end
end
else begin
if(pwm_with == T_10K)begin
flag <= 1;
end
else begin
pwm_with <= pwm_with + 1'b1;
end
end
end
else begin
pwm_with <= pwm_with;
end
end
/**********************************************************************/
always@ (posedge clk or negedge rst_n)begin
if(!rst_n)begin
pwm_out <= 1'b0;
end
else if(pwm_count <= pwm_with)begin
pwm_out <= 1'b1;
end
else begin
pwm_out <= 1'b0;
end
end
endmodule [/mw_shl_code]
测试代码
[mw_shl_code=c,true]`timescale 1 ns/ 1 ns
module pwm_tb();
reg clk;
reg rst_n;
wire pwm_out;
parameter CYCLK = 20;
parameter RST_TIME = 3;
pwm_control UUT(
.clk(clk),
.rst_n(rst_n),
.pwm_out(pwm_out)
);
initial begin
clk = 0;
forever
#(CYCLK / 2)
clk = ~clk;
end
initial begin
rst_n = 1;
#2;
rst_n =0;
#(RST_TIME);
rst_n = 1;
end
endmodule
仿真波形[/mw_shl_code]
[mw_shl_code=c,true]
[/mw_shl_code]
[/mw_shl_code]
[mw_shl_code=c,true]
[/mw_shl_code]
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发表于 2015-4-1 19:44:11
发表于 2015-4-1 23:31:56
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