新手上路
- 积分
- 43
- 金钱
- 43
- 注册时间
- 2014-12-24
- 在线时间
- 1 小时
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经过一段时间的调试,我发现数据手册中的一些描述和实际情况是不同的,在此和大家分享一下;针对SR寄存器中的TXE位和TC位,数据手册中的描述如下:
Bit 7TXE: Transmit data register empty
This bit is set by hardware when the content of the TDR register has been transferred into
the shift register. An interrupt is generated if the TXEIE bit =1 in the USART_CR1 register. It
is cleared by a write to the USART_DR register.
0: Data is not transferred to the shift register
1: Data is transferred to the shift register)
Note: This bit is used during single buffer transmission.
Bit 6TC: Transmission complete
This bit is set by hardware if the transmission of a frame containing data is complete and if
TXE is set. An interrupt is generated if TCIE=1in the USART_CR1 register. It is cleared by
a software sequence (a read from the USART_SR register followed by a write to the
USART_DR register). The TC bit can also be cleared by writing a '0' to it. This clearing
sequence is recommended only for multibuffer communication.
0: Transmission is not complete
1: Transmission is complete
大家调试的时候会发现,一开始TC和TXE位就一直是1的,只要相应的位TCIE和TXEIE位是1 ,就可以产生相应的中断,黄色部分的描述是
这两位是可以通过上述软件操作清0的,但是事实上,TC和TXE是不能通过黄色字部分的操作清0,如果不手动清0,他们将一直是1,
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