always@(posedge fpga_clk or negedge rst_n )
begin
if(!rst_n)
begin
master_state1 <=1'b1;
// master_state2 <=1'b1;
end
else begin
master_state1<=i2c_sda;
// master_state2<=master_state1;
end
end
always@(posedge fpga_clk or negedge rst_n )
begin
if(!rst_n)
begin
slaver_state1 <=1'b1;
// master_state2 <=1'b1;
end
else begin
slaver_state1<=i2c_m_sda;
// master_state2<=master_state1;
end
end
always@(posedge fpga_clk or negedge rst_n )
begin
if(!rst_n)
dir<=0;
else begin
if(master_state1==0&&slaver_state1==1)
dir<=0;
else if(master_state1==1&&slaver_state1==0)
dir<=1;
else dir<=0;
end
end