** Note: (vsim-3812) Design is being optimized...
#
# ** Fatal: Internal Error - vopt returned success but vsim could not find a design to simulate!. Please contact customer support for further assistance.
#
# Error loading design
# Error: Error loading design
# Pausing macro execution
# MACRO ./flow_led_run_msim_rtl_verilog.do PAUSED at line 40
do flow_led_run_msim_rtl_verilog.do
手动仿真不优化时没问题
但是在quartus中运行RTL仿真就报错
/2 
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发表于 2019-4-14 11:47:28
发表于 2019-4-15 02:13:40
