时序约束？这警告怎么解决？

MY40130064

Warning (332060): Node: sysclk:mysysclk|ic2_100khz was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: sysclk:mysysclk|mclk1m was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: sysclk:mysysclk|mck10k was determined to be a clock but was found without an associated clock assignment.

pll产生mclk2m，分频后产生100KHZ   信号用。

SDC

# Clock constraints

create_clock -name {clk_48m} -period 20.833 -waveform { 0.000 10.410 } [get_ports {clk_48M}]

#create_clock -name "clk_48m" -period 20.833ns [get_ports {clk_48M}]

#create_clock -name {sysclk} -period 20.000 -waveform { 0.000 10.000 } [get_ports {sysclk}]
# Automatically constrain PLL and other generated clocks
derive_pll_clocks -create_base_clocks

# Automatically calculate clock uncertainty to jitter and other effects.
derive_clock_uncertainty



代码

altpll0 pll0(
                                        .inclk0(clk_in),
                                        .c0(mclk12m),
                                        .c1(mclk24m_180),
                                        .c2(mclk12m_90),
                                        .c3(mclk48m),
                                        .c4(mclk2m));


//******************************************************************************
//                              I2C模块100KHZ         
//******************************************************************************       

reg[3:0] clk100kDiv;
always@(posedge mclk2m)   
begin
        if (!clk_in)
                 begin       
                        clk100kDiv <= 'b0;
                        ic2_100khz <= 'b0;
                end
           else       
           begin          
                        if( clk100kDiv == 4'd9)
                        begin
                                ic2_100khz  <= ~ic2_100khz ;       
                                clk100kDiv <= 4'd0;
                        end       
                        else       
                                clk100kDiv  <= clk100kDiv +  4'd1;       
                end
end

正点原子

帮顶

siudya

能把这个模块整个代码放上来吗，不知道输入输出是什么

天天mdk

楼主最后咋解决的？我也碰到这个问题了。

MY40130064

天天mdk 发表于 2021-8-9 12:04
楼主最后咋解决的？我也碰到这个问题了。

不用管它 让它警告就行了 头像不错啊