quartus ii 编译成功，资源却占用0%

topleader · 发表于 2018-2-2 11:32:52

  /********************************************以上是一个VGA 显示的字符的代码逻辑，编译没有ERROR ，当编译后占用的寄存器资源却为0%；，利用了FPGA 里的PLL 和ROM，通过读取ROM的数据送到VGA接口显示，采用的是1024X768的分辨率屏
******************************************************************************************/
module word_test(input clk,
input rst_n,
output [4:0]data_r,
output [5:0]data_g,
output [4:0]data_b,
output h_signal,
output v_signal
);

//Horizontal Define
parameter LinePeriod = 1344;
parameter H_SyncyPulse = 136;
parameter H_BackProch = 160;
parameter H_ActivePix = 1024;
parameter H_FrontProch = 24;
parameter H_start = 296;
parameter H_end = 1320;

//Vertical Define
parameter VerticalPeriod = 806;
parameter VyncyPulse = 6;
parameter V_BackProch = 29;
parameter V_ActivePix = 768;
parameter V_FrontProch = 3;
parameter V_Start  = 35;
parameter V_End = 803;

//Register Definiton
reg [10:0]H_cnt;
reg [9:0]V_cnt;
reg hsyncy;
reg vsyncy;
reg h_mask;
reg v_mask;

wire vga_clock;

parameter H_VaildArea = 400;//default 32 bits
parameter V_VaildArea = 200;
parameter V_VaildAddress = 375;

//counter Loop
always@(posedge vga_clock)
begin
if(~rst_n)H_cnt <= 1;
else if(H_cnt == LinePeriod) H_cnt <= 1;
else H_cnt <= H_cnt + 1 ;
end

always@(posedge vga_clock)
begin
if(~rst_n)hsyncy <= 1'b1;
else if(H_cnt == 1)hsyncy <= 1'b0;
else if(H_cnt == H_SyncyPulse) hsyncy <= 1'b1;

if(1'b0)h_mask <= 1'b0;
else if(H_cnt == H_start) h_mask <= 1'b1;
else if(H_cnt == H_end) h_mask <= 1'b0;
end

//Generate Vertical Direction Counter
always@(posedge vga_clock)
if(~rst_n) V_cnt <= 1;
else if(V_cnt == LinePeriod)V_cnt <= V_cnt + 1;
else if(V_cnt == VerticalPeriod) V_cnt <= 1;

//Generate Vertical Direction Wave
always@(posedge vga_clock)
begin
if(~rst_n) vsyncy <= 1'b1;
else if(V_cnt == 1) vsyncy <= 1'b0;
else if(V_cnt == VyncyPulse) vsyncy <= 1'b1;

//if(~rst_n) v_mask <= 1'b0;
if(1'b0) v_mask <= 1'b0;
else if(V_cnt == V_Start) v_mask <= 1'b1;
else if(V_cnt == V_End ) v_mask <= 1'b0;

end

reg [4:0]x_cnt0; //
reg [4:0]x_cnt1;

reg [10:0]x_address0;//first byte Address
reg [10:0]x_address1;//second byte Address

wire x_word0;// Array : ALEX
wire x_word1;

wire y_word0;// Array : ALEX
wire y_word1;

wire pre_word0;// Array : ALEX
wire pre_word1;

assign x_word0 = (H_cnt >= H_VaildArea && H_cnt < H_VaildArea + 40)? 1'b1: 1'b0;
assign y_word0 = (V_cnt >= V_VaildArea && V_cnt < V_VaildArea + 75)? 1'b1: 1'b0;
assign pre_word0 = (H_cnt>= H_VaildArea-2 && H_cnt < H_VaildArea +38)? 1'b1: 1'b0;

assign x_word1 = ((H_cnt >= H_VaildArea +100) && H_cnt < H_VaildArea + 140)? 1'b1: 1'b0;
assign y_word1 = (V_cnt >= V_VaildArea && V_cnt < V_VaildArea + 75)? 1'b1: 1'b0;
assign pre_word1 = (H_cnt>= H_VaildArea-2 + 100 && H_cnt < H_VaildArea +140-2 )? 1'b1: 1'b0;

//Remap Address to ROM
always@(posedge vga_clock)
begin
if(~rst_n)
begin
x_cnt0 <= 0;
x_cnt1 <= 0;

x_address0 <= 0;
x_address1 <= 375;//375

end

else begin
if(vsyncy == 1'b0)
begin

x_address0 <= 0;
                     x_address1 <=375;//

x_cnt0 <= 0;
x_cnt1 <= 0;

end

else if((y_word0==1'b1)&&(pre_word0 == 1'b1) )begin // 0 byte address
if(x_cnt0 == 7) begin
x_address0 <= x_address0 + 1'b1;
x_cnt0 <= 0;
end
else begin
x_cnt0 <= x_cnt0 + 1'b1;
x_address0 <= x_address0;
end
end

else if((y_word1==1'b1)&&(pre_word1 == 1'b1) )begin
if(x_cnt1 == 7)
begin
x_cnt1 <= 0;
x_address1 <= x_address1 + 1'b1 ;
end
else
begin
x_address1 <= x_address1;
x_cnt1 <= x_cnt1 + 1'b1;
end
end

else begin
x_address0 <= x_address0;
x_address1 <= x_address1;
///x_address2 <= x_address2;
///x_address3 <= x_address3;
x_cnt0 <= 0;//clear 0
x_cnt1 <= 0;
///x_cnt2 <= 0;
///x_cnt3 <= 0;
end
end

end

reg [4:0]x_data0;
reg [4:0]x_data1;

always@(posedge vga_clock)
begin
if(~rst_n)
begin
x_data0 <= 7;//Clear 0
x_data1 <= 7;//

end
else begin
if(vsyncy == 1'b0)//
begin
x_data0 <= 7;
x_data1 <= 7;

   end

else if((x_word0== 1'b1) && (y_word0== 1'b1))
begin
if(x_data0==0)
x_data0 <= 7;
else
x_data0 <= x_data0 - 1'b1;
end

else if( (x_word1== 1'b1) && (y_word1== 1'b1))
begin
if(x_data1== 0)
x_data1 <= 7;
else
x_data1 <= x_data1 - 1'b1;
end

else begin
x_data0 <= 7;
x_data1 <= 7;
end

end
end

/*sys_pll PLL (
.areset(~rst_n),
.inclk0(clk),
.c0(vga_clock),
.locked()
);
*/
wire [4:0]out_data1;
wire [4:0]out_data2;
wire [4:0]data_select;

assign out_data1 = {5{rom_data[x_data0]}};
assign out_data2 = {5{rom_data[x_data1]}};

assign data_select = (x_word0 == 1'b1) ? out_data1 : out_data2;

wire [10:0] rom_address ;
wire [7:0] rom_data;

assign rom_address = (x_word0 == 1'b1) ? x_address0 : x_address1;

sys_rom m2(
.address(rom_address),
.clock(vga_clock),
.q(rom_data)
);

assign h_signal = hsyncy;
assign v_signal = vsyncy ;

assign data_r = (((y_word0 ==1'b1)&&(x_word0==1'b1)) | ((y_word1==1'b1 && (x_word1 == 1'b1)))) ? data_select : 5'b00000;
assign data_g = (h_mask & v_mask ) ? 6'b000011 : 6'b000000;
assign data_b = (h_mask & v_mask ) ? 5'b00011 : 5'b00000;

sys_pll m1 (
.areset(~rst_n),
.inclk0(clk),
.c0(vga_clock),
.locked()
);

endmodule

/*********************************************/
以上是一个VGA 显示的字符的代码逻辑，编译没有ERROR ，当编译后占用的寄存器资源却为0%；
编译提示如下：
Warning (14284): Synthesized away the following node(s):
Warning (14285): Synthesized away the following RAM node(s):
Warning (14320): Synthesized away node "sys_rom:m2|altsyncram:altsyncram_component|altsyncram_j491:auto_generated|q_a[0]"
Warning (14320): Synthesized away node "sys_rom:m2|altsyncram:altsyncram_component|altsyncram_j491:auto_generated|q_a[1]"
Warning (14320): Synthesized away node "sys_rom:m2|altsyncram:altsyncram_component|altsyncram_j491:auto_generated|q_a[2]"
Warning (14320): Synthesized away node "sys_rom:m2|altsyncram:altsyncram_component|altsyncram_j491:auto_generated|q_a[3]"
Warning (14320): Synthesized away node "sys_rom:m2|altsyncram:altsyncram_component|altsyncram_j491:auto_generated|q_a[4]"
Warning (14320): Synthesized away node "sys_rom:m2|altsyncram:altsyncram_component|altsyncram_j491:auto_generated|q_a[5]"
Warning (14320): Synthesized away node "sys_rom:m2|altsyncram:altsyncram_component|altsyncram_j491:auto_generated|q_a[6]"
Warning (14320): Synthesized away node "sys_rom:m2|altsyncram:altsyncram_component|altsyncram_j491:auto_generated|q_a[7]"

DeBug了很久，没有解决；求各位帮忙解答下