求助Verilog函数的用法

as564335sa · 发表于 2013-6-28 11:33:55

Verilog用函数方式描述一个4选1选择器，function里的过程语句该怎么写啊我这么写报错：functions can't contain non-blocking assignments

module MUX4(a,b,c,d,s0,s1,y);
input s0,s1;
input a,b,c,d;
output y;
reg y;
function MUX;
input s0,s1;input a,b,c,d;
begin
if(s0==0&&s1==0) MUX<=a;
if(s0==0&&s1==1) MUX<=b;
if(s0==1&&s1==0) MUX<=c;
if(s0==1&&s1==0) MUX<=d;
end
endfunction
always@(a,b,c,d,s0,s1,y) begin
y=MUX(a,b,c,d,s0,s1);
end
endmodule