DSP5509通过cpld控制0v7670摄像头，以帧信号触发外部中断2进行fifo的写入与读取。但出现异常怎么回事？

碳酸钙

[mw_shl_code=c,true] #include <csl.h> #include <csl_pll.h> #include <csl_emif.h> #include <csl_chip.h> #include <stdio.h> #include "led.h" #include "11.h" #include <csl_irq.h> /*锁相环的设置*/ PLL_Config myConfig = { 0, //IAI: the PLL locks using the same process that was underway //before the idle mode was entered 1, //IOB: If the PLL indicates a break in the phase lock, //it switches to its bypass mode and restarts the PLL phase-locking //sequence 12, //PLL multiply value; multiply 12 times 2 //Divide by 2 PLL divide value; it can be either PLL divide value //(when PLL is enabled), or Bypass-mode divide value //(PLL in bypass mode, if PLL multiply value is set to 1) }; /*SDRAM的EMIF设置*/ EMIF_Config emiffig = { 0x221, //EGCR : the MEMFREQ = 00,the clock for the memory is equal to cpu frequence // the WPE = 0 ,forbiden the writing posting when we debug the EMIF // the MEMCEN = 1,the memory clock is reflected on the CLKMEM pin // the NOHOLD = 1,HOLD requests are not recognized by the EMIF 0xFFFF, //EMI_RST: any write to this register resets the EMIF state machine 0x1fff, //CE0_1: CE0 space control register 1 0x1fff 0x00ff, //CE0_2: CE0 space control register 2 0x00ff 0x00ff, //CE0_3: CE0 space control register 3 0x00ff 0x1000, //CE1_1: CE0 space control register 1 // Asynchronous, 16Bit 0x0000, //CE1_2: CE0 space control register 2 0x00ff, //CE1_3: CE0 space control register 3 0x1FFF, //CE2_1: CE0 space control register 1 // Asynchronous, 16Bit 0xFFFF, //CE2_2: CE0 space control register 2 0x00FF, //CE2_3: CE0 space control register 3 0x1fff, //CE3_1: CE0 space control register 1 0x00ff, //CE3_2: CE0 space control register 2 0x00ff, //CE3_3: CE0 space control register 3 0x2911, //SDC1: SDRAM control register 1 // TRC = 8 从刷新命令REFR到REFR/MRS/ACTV命令间隔CLKMEM周期数 // SDSIZE = 0 SDRAM宽度为16位宽; // SDWID = 0 SDRSM容量为64M位； // RFEN = 1 允许刷新； // TRCD = 2 从ACTV（打开所选择边界和所选择行）命令到READ/WRITE命令CLKMEM周期数 // TRP = 2 从DCAB命令到REFR/ACTV/MRS命令CLKMEM周期数 0x0410, //SDPER : SDRAM period register // 7ns *4096 0x07FF, //SDINIT: SDRAM initialization register // any write to this register to init the all CE spaces, // do it after hardware reset or power up the C55x device 0x0131 //SDC2: SDRAM control register 2 // SDACC = 0; // TMRD = 01; // TRAS = 0101; // TACTV2ACTV = 0001; }; CSLBool b; Uint16 eventId0; int old_intm; interrupt void int2(void); extern void VECSTART(void); void INTconfig() { /* Temporarily disable all maskable interrupts */ IRQ_setVecs((Uint32)(&VECSTART)); //插入表头 /* Temporarily disable all maskable interrupts */ old_intm = IRQ_globalDisable(); //关闭可屏蔽中断 /* Get Event Id associated with External INT1(8019), for use with */ eventId0 = IRQ_EVT_INT2; //定义事件 /* Clear any pending INT2 interrupts */ IRQ_clear(eventId0); //清中断 /* Place interrupt service routine address at */ /* associated vector location */ IRQ_plug(eventId0,&int2); //将中断向量表和c程序联系起来 /* Enable INT1(8019) interrupt */ IRQ_enable(eventId0); // 使能 /* Enable all maskable interrupts */ IRQ_globalEnable(); } unsigned int Vsync_Flag=0; unsigned int i,j; unsigned char imgdat; unsigned char datl,dath; main() { /*初始化CSL库*/ CSL_init(); /*EMIF为全EMIF接口*/ CHIP_RSET(XBSR,0x0a01); /*设置系统的运行速度为144MHz*/ PLL_config(&myConfig); /*初始化DSP的EMIF*/ EMIF_config(&emiffig); TFTinit(); //TFT_Clear(RED); TFT_Clear(WHITE); while(1!=Cmos7670_init()); //CMOS初始化 //Vsync_Flag=0; Address_set(0,0,239,319); //Address_set(0,0,LCD_W-1,LCD_H-1); INTconfig(); while(1) { } } interrupt void int2(void) { //unsigned int Vsync_Flag; IRQ_disable(eventId0); //关闭中断 Vsync_Flag++; if(Vsync_Flag==1) { //OV7670_Contr=FIFO_WEN|0x01; //FIFO_WEN=1; 允许CMOS写入FIFO OV7670_Contr=FIFO_WRST_L;//FIFO_WRST=0; //reset the write address复位写指针........... Delay(100); OV7670_Contr=FIFO_WRST_H;//FIFO_WRST=1; 写指针 OV7670_Contr=FIFO_WEN_H; //FIFO_WEN=1; 允许CMOS写入FIFO Vsync_Flag++; } else if(Vsync_Flag==2) { OV7670_Contr=FIFO_WEN_L; //FIFO_WEN=0; 禁止CMOS写入FIFO //IRQ_disable(eventId0); OV7670_Contr=FIFO_RRST_L;//FIFO_RRST=0;reset the write address 开始复位读指针 //at least one RCK clock is needed to make sure OV7670_Contr=FIFO_RCLK_L; //FIFO_RCLK=0; OV7670_Contr=FIFO_RCLK_H; //FIFO_RCLK=1; OV7670_Contr=FIFO_RCLK_L; //FIFO_RCLK=0; OV7670_Contr=FIFO_RCLK_H; //FIFO_RCLK=1; OV7670_Contr=FIFO_RRST_H;//FIFO_RRST=1; 复位读指针结束 OV7670_Contr=FIFO_OE_H; //FIFO_OE=1; 关断控制 Delay(1); OV7670_Contr=FIFO_OE_L; //FIFO_OE=0; Delay(1); Address_set(0,0,239,319); //Address_set(0,0,LCD_W-1,LCD_H-1); for(j=0; j<240; j++) //QVGA format,240 lines;320dots every line￡?153600 8bit data { for(i=0; i<320;i++) { OV7670_Contr=FIFO_RCLK_L; //FIFO_RCLK=0 dath=OV7670_DATA; OV7670_Contr=FIFO_RCLK_H; //FIFO_RCLK=1 if(i<240)dath=dath<<8; OV7670_Contr=FIFO_RCLK_L; //FIFO_RCLK=0 datl=OV7670_DATA; OV7670_Contr=FIFO_RCLK_H; //FIFO_RCLK= if(i<240) { //datl=OV7670_DATA; imgdat=dath|datl; //Address_set(j,i,239,319); TFT_WR_img(imgdat); } } } OV7670_Contr=FIFO_OE_H; //FIFO_OE=1; OV7670_Contr=FIFO_WEN_L; //FIFO_WEN=0; Vsync_Flag=0; //IRQ_enable(eventId0); Delay(1); } IRQ_enable(eventId0); } [/mw_shl_code]