ZYNQ的FIFO那一章节联合仿真失败

蔡纪龙

# Top level modules:
#         fifo_generator_vlog_beh
# End time: 21:05:39 on Dec 20,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# ** Error: Model Technology ModelSim SE-64 vcom 10.4 Compiler 2014.12 Dec  3 2014
# Start time: 21:05:39 on Dec 20,2023
# vcom -93 -work fifo_generator_v13_2_5 ../../../../ip_fifo.ip_user_files/ipstatic/hdl/fifo_generator_v13_2_rfs.vhd
# -- Loading package STANDARD
# ** Error: ../../../../ip_fifo.ip_user_files/ipstatic/hdl/fifo_generator_v13_2_rfs.vhd(79): near "AES128-CBC": Unknown session key in protected region
# ** Error: ../../../../ip_fifo.ip_user_files/ipstatic/hdl/fifo_generator_v13_2_rfs.vhd(80): VHDL Compiler exiting
# End time: 21:05:40 on Dec 20,2023, Elapsed time: 0:00:01
# Errors: 2, Warnings: 0
# child process exited abnormally
# Error in macro ./tb_ip_fifo_compile.do line 23
# Model Technology ModelSim SE-64 vcom 10.4 Compiler 2014.12 Dec  3 2014
# Start time: 21:05:39 on Dec 20,2023
# vcom -93 -work fifo_generator_v13_2_5 ../../../../ip_fifo.ip_user_files/ipstatic/hdl/fifo_generator_v13_2_rfs.vhd
# -- Loading package STANDARD
# ** Error: ../../../../ip_fifo.ip_user_files/ipstatic/hdl/fifo_generator_v13_2_rfs.vhd(79): near "AES128-CBC": Unknown session key in protected region
# ** Error: ../../../../ip_fifo.ip_user_files/ipstatic/hdl/fifo_generator_v13_2_rfs.vhd(80): VHDL Compiler exiting
# End time: 21:05:40 on Dec 20,2023, Elapsed time: 0:00:01
# Errors: 2, Warnings: 0
# child process exited abnormally
#     while executing
# "exec <nul: {D:\Modelsim\win64\vcom.EXE} -93 -work fifo_generator_v13_2_5 ../../../../ip_fifo.ip_user_files/ipstatic/hdl/fifo_generator_v13_2_rfs.vhd"
#     ("uplevel" body line 1)
#     invoked from within
# "uplevel 1 exec $redir $new [lrange $args 1 end]"
#     (procedure "::unknown" line 47)
#     invoked from within
# "D:\\Modelsim\\win64\\vcom  -93 -work fifo_generator_v13_2_5  \
# "../../../../ip_fifo.ip_user_files/ipstatic/hdl/fifo_generator_v13_2_rfs.vhd" \
# "

QinQZ

看上面的报错信息，提示是vhdl代码的错误，是不是创建工程或者仿真文件时仿真选项是VHDL，而不是Verilog