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ZYNQ的FIFO那一章节,按照官方代码无法联仿真

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2020-7-2
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发表于 2023-12-20 20:40:41 | 显示全部楼层 |阅读模式
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点击仿真之后,出现问题,无法联合仿真。
我用了他官方的工程文件也是一样呢


# Top level modules:
#         fifo_generator_vlog_beh
# End time: 20:35:35 on Dec 20,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# ** Error: Model Technology ModelSim SE-64 vcom 10.4 Compiler 2014.12 Dec  3 2014
# Start time: 20:35:35 on Dec 20,2023
# vcom -93 -work fifo_generator_v13_2_5 ../../../../ip_fifo.ip_user_files/ipstatic/hdl/fifo_generator_v13_2_rfs.vhd
# -- Loading package STANDARD
# ** Error: ../../../../ip_fifo.ip_user_files/ipstatic/hdl/fifo_generator_v13_2_rfs.vhd(79): near "AES128-CBC": Unknown session key in protected region
# ** Error: ../../../../ip_fifo.ip_user_files/ipstatic/hdl/fifo_generator_v13_2_rfs.vhd(80): VHDL Compiler exiting
# End time: 20:35:35 on Dec 20,2023, Elapsed time: 0:00:00
# Errors: 2, Warnings: 0
# child process exited abnormally
# Error in macro ./tb_ip_fifo_compile.do line 36
# Model Technology ModelSim SE-64 vcom 10.4 Compiler 2014.12 Dec  3 2014
# Start time: 20:35:35 on Dec 20,2023
# vcom -93 -work fifo_generator_v13_2_5 ../../../../ip_fifo.ip_user_files/ipstatic/hdl/fifo_generator_v13_2_rfs.vhd
# -- Loading package STANDARD
# ** Error: ../../../../ip_fifo.ip_user_files/ipstatic/hdl/fifo_generator_v13_2_rfs.vhd(79): near "AES128-CBC": Unknown session key in protected region
# ** Error: ../../../../ip_fifo.ip_user_files/ipstatic/hdl/fifo_generator_v13_2_rfs.vhd(80): VHDL Compiler exiting
# End time: 20:35:35 on Dec 20,2023, Elapsed time: 0:00:00
# Errors: 2, Warnings: 0
# child process exited abnormally
#     while executing
# "exec <nul: {D:\Modelsim\win64\vcom.EXE} -93 -work fifo_generator_v13_2_5 ../../../../ip_fifo.ip_user_files/ipstatic/hdl/fifo_generator_v13_2_rfs.vhd"
#     ("uplevel" body line 1)
#     invoked from within
# "uplevel 1 exec $redir $new [lrange $args 1 end]"
#     (procedure "::unknown" line 47)
#     invoked from within
# "D:\\Modelsim\\win64\\vcom  -93 -work fifo_generator_v13_2_5  \
# "../../../../ip_fifo.ip_user_files/ipstatic/hdl/fifo_generator_v13_2_rfs.vhd" \
# "
ModelSim>

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