vivado不能仿真，出现错误

xiyongzhen

仿真出现错误，这是什么问题，我两台电脑都是按照视频教程安装的vivado，都是这个错误

QinQZ

错误提示的.log文件，可以根据提示的路径，打开这个文件，看看具体错误类型

rike0909

我也碰到同样的问题，无法解决，我把LOG 文件上传，看看有谁能帮吗解决

#-----------------------------------------------------------
# Vivado v2019.2 (64-bit)
# SW Build 2708876 on Wed Nov  6 21:40:23 MST 2019
# IP Build 2700528 on Thu Nov  7 00:09:20 MST 2019
# Start of session at: Mon May 27 11:01:43 2024
# Process ID: 18044
# Current directory: C:/Users/P5080/Desktop/tst/vivado_test/project_2
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent15456 C:\Users\P5080\Desktop\tst\vivado_test\project_2\project_2.xpr
# Log file: C:/Users/P5080/Desktop/tst/vivado_test/project_2/vivado.log
# Journal file: C:/Users/P5080/Desktop/tst/vivado_test/project_2\vivado.jou
#-----------------------------------------------------------
start_gui
open_project C:/Users/P5080/Desktop/tst/vivado_test/project_2/project_2.xpr
CRITICAL WARNING: [Project 1-19] Could not find the file 'E:/fpga实例源码/1_Verilog/1_Verilog/1_Verilog/1_led/prj/tb_led_behav.wcfg'.
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.2/data/ip'.
update_compile_order -fileset sources_1
reset_run impl_1
launch_runs impl_1 -jobs 8
[Mon May 27 11:02:33 2024] Launched impl_1...
Run output will be captured here: C:/Users/P5080/Desktop/tst/vivado_test/project_2/project_2.runs/impl_1/runme.log
launch_simulation
Command: launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/P5080/Desktop/tst/vivado_test/project_2/project_2.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-54] Inspecting design source files for 'tb_led' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/P5080/Desktop/tst/vivado_test/project_2/project_2.sim/sim_1/behav/xsim'
"xvlog --incr --relax -prj tb_led_vlog.prj"
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/fpga实例源码/1_Verilog/1_Verilog/1_Verilog/1_led/rtl/led.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module led
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/fpga实例源码/1_Verilog/1_Verilog/1_Verilog/1_led/sim/tb/tb_led.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module tb_led
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/P5080/Desktop/tst/vivado_test/project_2/project_2.sim/sim_1/behav/xsim'
"xelab -wto 0eb3b2d2b8f6413d8863613655db2da1 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot tb_led_behav xil_defaultlib.tb_led xil_defaultlib.glbl -log elaborate.log"
Vivado Simulator 2019.2
Copyright 1986-1999, 2001-2019 Xilinx, Inc. All Rights Reserved.
Running: D:/Xilinx/Vivado/2019.2/bin/unwrapped/win64.o/xelab.exe -wto 0eb3b2d2b8f6413d8863613655db2da1 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot tb_led_behav xil_defaultlib.tb_led xil_defaultlib.glbl -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
Completed static elaboration
Starting simulation data flow analysis
WARNING: [XSIM 43-4099] "E:/fpga实例源码/1_Verilog/1_Verilog/1_Verilog/1_led/rtl/led.v" Line 19. Module led doesn't have a timescale but at least one module in design has a timescale.
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module xil_defaultlib.led
Compiling module xil_defaultlib.tb_led
Compiling module xil_defaultlib.glbl
ERROR: [XSIM 43-3409] Failed to compile generated C file xsim.dir/tb_led_behav/obj/xsim_1.c.
ERROR: [XSIM 43-3915] Encountered a fatal error. Cannot continue. Exiting...
INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
INFO: [USF-XSim-99] Step results log file:'C:/Users/P5080/Desktop/tst/vivado_test/project_2/project_2.sim/sim_1/behav/xsim/elaborate.log'
ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'C:/Users/P5080/Desktop/tst/vivado_test/project_2/project_2.sim/sim_1/behav/xsim/elaborate.log' file for more information.
ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.