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发表于 2022-12-14 23:29:26
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- SEGGER J-Link Commander V7.66a (Compiled May 19 2022 15:19:28)
- DLL version V7.66a, compiled May 19 2022 15:18:08
- Connecting to J-Link via USB...O.K.
- Firmware: J-Link V11 compiled Apr 27 2041 16:36:21
- Hardware version: V11.00
- S/N: 941000024
- License(s): GDB, JFlash, FlashDL, RDI, FlashBP
- VTref=3.322V
- Type "connect" to establish a target connection, '?' for help
- J-Link>connect
- Please specify device / core. <Default>: MCIMX6G0
- Type '?' for selection dialog
- Device>
- Please specify target interface:
- J) JTAG (Default)
- S) SWD
- T) cJTAG
- TIF>
- Device position in JTAG chain (IRPre,DRPre) <Default>: -1,-1 => Auto-detect
- JTAGConf>
- Specify target interface speed [kHz]. <Default>: 4000 kHz
- Speed>
- Device "MCIMX6G0" selected.
- Connecting to target via JTAG
- ConfigTargetSettings() start
- J-Link script: Setting up AP map
- ConfigTargetSettings() end
- TotalIRLen = 13, IRPrint = 0x0101
- At least one of the connected devices is not JTAG compliant (IEEE Std 1149.1, 7.1.1.d, IR-cells). (NumDevices = 3, NumBitsSet = 2)
- JTAG chain detection found 3 devices:
- #0 Id: 0x5BA00477, IRLen: 04, CoreSight JTAG-DP
- #1 Id: 0x00000001, IRLen: 05, Unknown device
- #2 Id: 0x088C101D, IRLen: 04, JTAG-DP
- DPv0 detected
- AP map detection skipped. Manually configured AP map found.
- AP[0]: AHB-AP (IDR: Not set)
- AP[1]: APB-AP (IDR: Not set)
- Using preconfigured AP[1] as APB-AP
- AP[1]: APB-AP found
- ROMTbl[0][0]: CompAddr: 80001000 CID: B105900D, PID: 001BB961 TMC
- ROMTbl[0][1]: CompAddr: 80002000 CID: B105900D, PID: 004BB906 CTI
- ROMTbl[0][2]: CompAddr: 80003000 CID: B105900D, PID: 004BB912 TPIU
- ROMTbl[0][3]: CompAddr: 80004000 CID: B105F00D, PID: 001BB101 TSG
- ROMTbl[0][4]: CompAddr: 80020000 CID: B105100D, PID: 000BB4A7 ROM Table
- ROMTbl[1][0]: CompAddr: 80030000 CID: B105900D, PID: 005BBC07 Cortex-A7
- Found Cortex-A7 r0p5
- 6 code breakpoints, 4 data breakpoints
- Debug architecture ARMv7.1
- Data endian: little
- Main ID register: 0x410FC075
- I-Cache L1: 32 KB, 512 Sets, 32 Bytes/Line, 2-Way
- D-Cache L1: 32 KB, 128 Sets, 64 Bytes/Line, 4-Way
- Unified-Cache L2: 128 KB, 256 Sets, 64 Bytes/Line, 8-Way
- System control register:
- Instruction endian: little
- Level-1 instruction cache enabled
- Level-1 data cache disabled
- MMU disabled
- Branch prediction enabled
- Memory zones:
- Zone: Default Description: Default access mode
- Zone: AHB-AP (AP0) Description: DMA like acc. in AP0 addr. space
- Zone: APB-AP (AP1) Description: DMA like acc. in AP1 addr. space
- Cortex-A7 identified.
- J-Link>
复制代码 JLink可以,需要选择器件型号为MCIMX6G0
因为IMX6ULL器件型号就是这个,IMX6ULL应该是这个系列的总称
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