求FPGA驱动DS2431读写程序

SSWWKK · 发表于 2022-4-2 14:25:55

verilog语言 quartus软件 fpga做DS2431 读写程序正点开拓者开发板串口232调试，发送地址写数据，发送地址读数据。
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SSWWKK · 发表于 2022-4-2 14:25:56

void DQ_MODE_OUT( void )
{
GPIO_InitTypeDef GPIO_InitStructure;
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC,ENABLE);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
GPIO_Init( GPIOC, &GPIO_InitStructure );
}
void DQ_MODE_IN( void )
{
GPIO_InitTypeDef GPIO_InitStructure;
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC,ENABLE);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_Init( GPIOC, &GPIO_InitStructure );
}

//发送一字节
void bus_sendbyte(u8 dat)
{
u8 count;
DQ_MODE_OUT();
DQ_OUT=1;
for(count=0;count<8;count++)
{
if((dat&(0x01<<count))==0)
{
DQ_OUT=1;
DQ_OUT=0;
delay_us(65);
DQ_OUT=1;
delay_us(6);
}
else
{
DQ_OUT=1;
DQ_OUT=0;
delay_us(6);
DQ_OUT=1;
delay_us(65);
}
}
DQ_OUT=1;
DQ_MODE_IN();
delay_us(10000);
}
//接收一字节
uint8_t bus_getbyte(void)
{
uint8_t dat=0;
uint8_t count;
for(count=0;count<8;count++)
{
DQ_MODE_OUT() ;
DQ_OUT=1;
delay_us(1);
DQ_OUT=0;
delay_us(6);
DQ_OUT=1;
DQ_MODE_IN();
delay_us(10);
dat >>= 1;
if( DQ_READ==1 )
{
dat |= 0x80;
}
/*
if(DQ_READ==1)
{
dat|=(0x01<<count);
}
*/
delay_us(55);
}
delay_us(10000);
return dat;
}
//复位
u8 bus_reset(void)
{
DQ_MODE_OUT() ;
DQ_OUT=1;
delay_ms(5);
DQ_OUT=0;
delay_us(550);
DQ_OUT=1;
delay_us(100);
DQ_MODE_IN();
delay_us(10);
if(DQ_READ==0)
{
delay_us(500);
return 1;
}
else
{
return 0;
}
}
//*******************************************************************************//
int main(void)
{
u8 rs485buf[255];
u8 key;
delay_init();
RS485_Init(9600); //RS485
      //复位正常
key=bus_reset();
rs485buf[0]=key;
RS485_Send_Data(rs485buf,1);
//读序列号正常
bus_sendbyte(0x33);
for(i=0;i<8;i++)
{
rs485buf[i] = bus_getbyte();
}
RS485_Send_Data(rs485buf,8);
//写缓存 00 地址 8字节
key=bus_reset();
bus_sendbyte(0xCC);
bus_sendbyte(0x0F);
bus_sendbyte(0x00);
bus_sendbyte(0x00);
for(i=0;i<8;i++)
{
bus_sendbyte(i+16);
}
key=bus_getbyte();
rs485buf[0]=key;
      key=bus_getbyte();
rs485buf[1]=key;
RS485_Send_Data(rs485buf,2);
//读缓存省略
      //写入存储区
key=bus_reset();
bus_sendbyte(0xcc);
bus_sendbyte(0x55);
bus_sendbyte(0x00);
bus_sendbyte(0x00);
bus_sendbyte(0x07);
delay_ms(20);
      //读出正常
key=bus_reset();
bus_sendbyte(0xcc);
bus_sendbyte(0xf0);
bus_sendbyte(0x00);
bus_sendbyte(0x00);
for(i=0;i<8;i++)
{
rs485buf[i] = bus_getbyte();
}
RS485_Send_Data(rs485buf,8);
key=bus_reset();
}

gjs13030247996 · 发表于 2022-4-2 17:22:54

帮顶一下

SSWWKK · 发表于 2022-4-4 17:29:50

顶一下

SSWWKK · 发表于 2022-4-11 15:57:30

顶一下

SSWWKK · 发表于 2022-10-11 10:10:07

#define DQ_OUT PCout(11) //
#define DQ_READ PCin(11) //

SSWWKK · 发表于 2022-11-17 11:24:19

         wr_init:begin                            //初始化
            init_done <= 1'b0;
            case(flow_cnt)
4'd0:begin //发出550us复位脉冲
                     cnt_1us_en <= 1'b1;
                     if(cnt_1us < 20'd10)
                        dq_out <= 1'bz;
                     else begin
                        cnt_1us_en <= 1'b0;
                        dq_out <= 1'bz;
                        flow_cnt <= flow_cnt + 1'b1;
                     end
end
4'd1: begin //发出550us复位脉冲
                     cnt_1us_en <= 1'b1;
                     if(cnt_1us < 20'd600)
                        dq_out <= 1'b0;
                     else begin
                        cnt_1us_en <= 1'b0;
                        dq_out <= 1'bz;
                        flow_cnt <= flow_cnt + 1'b1;
                     end
end
               4'd2: begin //释放总线，等待110us
                     cnt_1us_en <= 1'b1;
                     if(cnt_1us < 20'd80)
                        dq_out <= 1'bz;
                     else
                        flow_cnt <= flow_cnt + 1'b1;
end
               4'd3: begin //检测响应信号
                     if(!dq)
                        flow_cnt <= flow_cnt + 1'b1;
                     else if(cnt_1us < 20'd200)
                        flow_cnt <= flow_cnt;
                     else
                        flow_cnt <= 1'b0;
end
               4'd4: begin //等待初始化结束
                     if(cnt_1us == 20'd600) begin
                        cnt_1us_en <= 1'b0;
                        init_done  <= 1'b1; //初始化完成
                        flow_cnt <= 4'd0;
                     end
                     else
                        flow_cnt <= flow_cnt;
end
                  default: flow_cnt <= 4'd0;
            endcase
         end

         wr_byte: begin                      //写字节状态（发送指令）
            if(wr_cnt <= 4'd7) begin
                  case (flow_cnt)
                     4'd0: begin
dq_out <= 1'b0; //拉低数据线，开始写操作
cnt_1us_en <= 1'b1; //启动计时器
flow_cnt <= flow_cnt + 1'b1;
end
                     4'd1: begin    //数据线拉低6us
if(cnt_1us < 20'd6)
dq_out <= 1'b0;
else
flow_cnt <= flow_cnt + 1'b1;
end
                     4'd2: begin
if(cnt_1us < 20'd60) //发送数据
dq_out <= wr_data[wr_cnt];
else if(cnt_1us < 20'd66)
dq_out <= 1'bz; //释放总线（发送间隔）
else
flow_cnt <= flow_cnt + 1'b1;
end
                     4'd3: begin    //发送1位数据完成
flow_cnt <= 0;
cnt_1us_en <= 1'b0;
wr_cnt <= wr_cnt + 1'b1;//写计数器加1
end
                     default : flow_cnt <= 0;
                  endcase
            end

         rd_byte: begin                      //接收8位数据
   if(rd_cnt  <= 4'd7) begin
                  case(flow_cnt)
                     4'd0: begin
cnt_1us_en <= 1'b0;
dq_out <= 1'b1;
flow_cnt <= flow_cnt + 1'b1;
end
                     4'd1: begin
cnt_1us_en <= 1'b1;
if(cnt_1us < 20'd6)
dq_out <= 1'b0; //拉低数据线，开始读操作
else
flow_cnt <= flow_cnt + 1'b1;
end
                     4'd2: begin
dq_out <= 1'bz; //释放总线并在16us内接收数据
if(cnt_1us == 20'd16) begin
rd_data <= {dq,rd_data[7:1]};
flow_cnt <= flow_cnt + 1'b1;
end
else
;
end
                     4'd3: begin
if (cnt_1us <= 20'd70) //读1位数据结束
dq_out <= 1'bz;
else begin
flow_cnt <= 4'd0;
rd_cnt <= rd_cnt + 1'b1;//读计数器加1
cnt_1us_en <= 1'b0;
end
end
                     default : flow_cnt <= 4'd0;
                  endcase
            end

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求FPGA驱动DS2431读写程序

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