ZYNQ7010 与DAC采用SPI通信，仿真没有问题，但上板后没有输出时钟

xt1030 · 发表于 2021-7-11 16:23:57

ZYNQ7010 与DAC采用SPI通信，仿真没有问题，但上板后没有输出时钟，有没有哪位大佬可以解决一下，万分感谢！！！
屏幕截图 2021-07-11 151636.png

顶层模块`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2021/07/10 23:43:50
// Design Name:
// Module Name: DAC_test
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////

//顶层模块
module DAC_test(
Clk, //模块时钟50M
Rst_n, //模块复位

DAC_CS_N,  //TLV5618的CS_N接口
DAC_DIN, //TLV5618的DIN接口
DAC_SCLK //TLV5618的SCLK接口
);
input Clk;
input Rst_n;

output DAC_CS_N;
output DAC_DIN;
output DAC_SCLK;

reg Start;
reg [15:0]r_DAC_DATA;
wire DAC_State;
wire [15:0]DAC_DATA;
wire Set_Done;

tlv5618 tlv5618(
.Clk(Clk),
.Rst_n(Rst_n),

.DAC_DATA(DAC_DATA),
.Start(Start),
.Set_Done(Set_Done),

.DAC_CS_N(DAC_CS_N),
.DAC_DIN(DAC_DIN),
.DAC_SCLK(DAC_SCLK),
.DAC_State(DAC_State)
);

ila_0 your_instance_name (
.clk(Clk), // input wire clk

.probe0(Rst_n), // input wire [0:0]  probe0
.probe1(DAC_CS_N), // input wire [0:0]  probe1
.probe2(DAC_DIN), // input wire [0:0]  probe2
.probe3(DAC_SCLK) // input wire [0:0]  probe3

);

always@(posedge Clk or negedge Rst_n)
if(!Rst_n)
r_DAC_DATA <= 16'd0;
else if(DAC_State)
r_DAC_DATA <= DAC_DATA;

always@(posedge Clk or negedge Rst_n)
if(!Rst_n)
Start <= 1'd0;
else if(r_DAC_DATA != DAC_DATA)
Start <= 1'b1;
else
Start <= 1'd0;

endmodule

// 驱动部分
module tlv5618(
Clk,
Rst_n,

DAC_DATA, //并行数据输入端
Start, //开始标志位
Set_Done, //完成标志位

DAC_CS_N, //片选
DAC_DIN, //串行数据送给ADC芯片
DAC_SCLK, //工作时钟SCLK
DAC_State //工作状态
);

parameter fCLK = 50; //时钟参数
parameter DIV_PARAM = 2; //分频参数

input Clk;
input Rst_n;
input [15:0] DAC_DATA;
input Start;
output reg Set_Done;

output reg DAC_CS_N;
output reg DAC_DIN;
output reg DAC_SCLK;
output DAC_State;

assign DAC_State = DAC_CS_N; //工作状态标志与片选信号相同

reg [15:0] r_DAC_DATA;

reg [3:0] DIV_CNT; //分频计数器
reg SCLK2X; //2倍SCLK的采样时钟

reg [5:0] SCLK_GEN_CNT; //SCLK生成暨序列机计数器

reg en; //转换使能信号

wire trans_done; //转换序列完成标志信号

always@(posedge Clk or negedge Rst_n)
if(!Rst_n)
en <= 1'b0;
else if(Start)
en <= 1'b1;
else if(trans_done)
en <= 1'b0; //转换完成后将使能关闭
else
en <= en;

//分频计数器
always@(posedge Clk or negedge Rst_n)
if(!Rst_n)
DIV_CNT <= 4'd0;
else if(en)begin
if(DIV_CNT == (DIV_PARAM - 1'b1)) //前面设置了分频系数为2，这里计数器能够容纳2拍时钟脉冲
DIV_CNT <= 4'd0;
else
DIV_CNT <= DIV_CNT + 1'b1;
end
else
DIV_CNT <= 4'd0;

//二分频
always@(posedge Clk or negedge Rst_n)
if(!Rst_n)
SCLK2X <= 1'b0;
else if(en && (DIV_CNT == (DIV_PARAM - 1'b1)))
SCLK2X <= 1'b1;
else
SCLK2X <= 1'b0;

//生成序列计数器，对SCLK脉冲进行计数
always@(posedge Clk or negedge Rst_n)
if(!Rst_n)
SCLK_GEN_CNT <= 6'd0;
else if(SCLK2X && en)begin //在高脉冲期间，累计拍数
if(SCLK_GEN_CNT == 6'd33)
SCLK_GEN_CNT <= 6'd0;
else
SCLK_GEN_CNT <= SCLK_GEN_CNT + 1'd1;
end
else
SCLK_GEN_CNT <= SCLK_GEN_CNT;

always@(posedge Clk or negedge Rst_n)
if(!Rst_n)
r_DAC_DATA <= 16'd0;
else if(Start) //收到开始发送命令时，寄存DAC_DATA值
r_DAC_DATA <= DAC_DATA;
else
r_DAC_DATA <= r_DAC_DATA;

//依次将数据移出到DAC芯片
always@(posedge Clk or negedge Rst_n)
if(!Rst_n)begin
DAC_DIN <= 1'b1;
DAC_SCLK <= 1'b0;
DAC_CS_N <= 1'b1;
end
else if(!Set_Done && SCLK2X) begin
case(SCLK_GEN_CNT)
0:
begin //高脉冲期间内，计数为0时了，打开片选使能，给予时钟上升沿，将最高位数据送给ADC芯片
DAC_CS_N <= 1'b0;
DAC_DIN <= r_DAC_DATA[15];
DAC_SCLK <= 1'b1;
end

1,3,5,7,9,11,13,15,17,19,21,23,25,27,29,31:
begin
DAC_SCLK <= 1'b0; //时钟低电平
end

2:  begin DAC_DIN <= r_DAC_DATA[14]; DAC_SCLK <= 1'b1; end
4:  begin DAC_DIN <= r_DAC_DATA[13]; DAC_SCLK <= 1'b1; end
6:  begin DAC_DIN <= r_DAC_DATA[12]; DAC_SCLK <= 1'b1; end
8:  begin DAC_DIN <= r_DAC_DATA[11]; DAC_SCLK <= 1'b1; end
10: begin DAC_DIN <= r_DAC_DATA[10]; DAC_SCLK <= 1'b1; end
12: begin DAC_DIN <= r_DAC_DATA[9];  DAC_SCLK <= 1'b1; end
14: begin DAC_DIN <= r_DAC_DATA[8];  DAC_SCLK <= 1'b1; end
16: begin DAC_DIN <= r_DAC_DATA[7];  DAC_SCLK <= 1'b1; end
18: begin DAC_DIN <= r_DAC_DATA[6];  DAC_SCLK <= 1'b1; end
20: begin DAC_DIN <= r_DAC_DATA[5];  DAC_SCLK <= 1'b1; end
22: begin DAC_DIN <= r_DAC_DATA[4];  DAC_SCLK <= 1'b1; end
24: begin DAC_DIN <= r_DAC_DATA[3];  DAC_SCLK <= 1'b1; end
26: begin DAC_DIN <= r_DAC_DATA[2];  DAC_SCLK <= 1'b1; end
28: begin DAC_DIN <= r_DAC_DATA[1];  DAC_SCLK <= 1'b1; end
30: begin DAC_DIN <= r_DAC_DATA[0];  DAC_SCLK <= 1'b1; end

32: DAC_SCLK <= 1'b1; //时钟拉高
33: DAC_CS_N <= 1'b1; //关闭片选
default:;
endcase
end

assign trans_done = (SCLK_GEN_CNT == 33) && SCLK2X;

always@(posedge Clk or negedge Rst_n)
if(!Rst_n)
Set_Done <= 1'b0;
else if(trans_done)
Set_Done <= 1'b1;
else
Set_Done <= 1'b0;

endmodule