简单的计数程序输出结果总是不对，求大牛帮忙

Gshop · 发表于 2019-7-13 17:09:41

我的程序是自己编写第一个通讯端口，其中FPGAtoAD_state是数据输出端口，PGAtoAD_clk_in是时钟输入端口，FPGAtoAD_data是数据输入端口，位宽为8位，FPGAtoAD_clk_out是时钟输出端口程序的主要流程如下：一开始是向上位机传一次数据，首先FPGAtoAD_clk_out拉低，等待上位机的PGAtoAD_clk_in时钟信号拉低表示上位机准备就绪，然后FPGAtoAD_clk_out置高，等待上位机的PGAtoAD_clk_in时钟信号置高就表示上位机读取成功，然后开始上位机向FPGA开始传输66次数据，每次传输以上位机的PGAtoAD_clk_in时钟信号拉低，然后FPGAtoAD_clk_out拉低表示准备好接受数据，之后PGAtoAD_clk_in时钟信号置高，等FPGAtoAD_clk_out也置高表示一次数据传输完成，反复66次
现在的问题就是FPGA计数有问题，用示波器看了，要不是到64次就不响应，要不就是中间丢两个数据，又或者是传输66次之后还在等待传输，有时偶尔能正常传输几次，但很快就又会漏数据。
求各位大牛帮我看看程序，看问题在哪
不胜感谢，小弟这里只有29个币，尽数奉上
系统时钟频率为50 MHz
具体程序如下

/*******************************************
FPGAtoAD
*******************************************/
reg [1:0] FPGAtoAD_rw;
reg [7:0] n;
reg [7:0] x;
parameter outime=50_000_000;
//reg ADCdata
/*
//
//FPGA_R
//
*/
// wire FPGAtoAD_clk_out_w;
// reg FPGAtoAD_clk_out_r;
//
// assign FPGAtoAD_clk_out= FPGAtoAD_rw ? FPGAtoAD_clk_out_r:FPGAtoAD_clk_out_w;
reg [3:0] FPGA_r_state;
parameter R_idel = 4'b0000;
parameter R_start = 4'b0001;
parameter R_GetD = 4'b0011;
parameter R_WaitD = 4'b0010;
parameter R_over = 4'b0110;
parameter R_Busy = 4'b1000;
/*
//
//FPGA_W
//
*/
reg [3:0] FPGA_w_state;
parameter W_idel = 4'b0000;
parameter w_start = 4'b0001;
parameter w_adbusy= 4'b1000;
parameter w_sclk_L= 4'b0011;
parameter w_buftim= 4'b0010;
parameter w_sdata = 4'b0110;
parameter w_sover = 4'b0111;
/*
//
//
//
*/
reg [7:0] inset_time;
reg [7:0] sent_time;
always [url=home.php?mod=space&uid=95564]@[/url] (posedge sys_clk or negedge sys_rst)
if(!sys_rst)
begin
FPGAtoAD_rw <= 2'b00;
inset_time<=8'd0;
sent_time<=8'd0;
end
else if(FPGAtoAD_rw == 2'b11)
begin
if(inset_time>=8'd100)
begin
FPGAtoAD_rw <= 2'b00;
inset_time<=8'd0;
end
else
inset_time<=inset_time+1'b1;
end
else if((FPGA_r_state == R_over)&(FPGAtoAD_rw == 2'b10))
begin
FPGAtoAD_rw <= 2'b11;
sent_time<=sent_time+1'b1;
end
else if((FPGA_w_state == w_sover)&(FPGAtoAD_rw == 2'b01))
FPGAtoAD_rw <= 2'b10;
else if(FPGAtoAD_rw == 2'b00)
FPGAtoAD_rw <= 2'b01;
else ;
reg [7:0] pre_state;
reg [25:0] to_cnt; //timeout
wire [7:0] n_add;
reg [7:0] n_buf;
assign n_add=n+1'b1;
always @ (posedge sys_clk or negedge sys_rst)
if(!sys_rst)
begin
FPGA_r_state <= R_idel;
FPGA_w_state <= W_idel;
//FPGAtoAD_clk_out <= 1'b1;
n <= 8'h0;
to_cnt <= 26'd0;
pre_state <= 8'd0;
FPGAtoAD_clk_out <= 1'b1;
FPGAtoAD_state <= 5'd0;
n_buf <= 8'h0;
for(x=8'd0;x<8'd66;x=x+1'b1)
ADCdata[x] <= 8'd0;
end
else if(FPGAtoAD_rw == 2'b10)
begin
case(FPGA_r_state)
R_idel:
if(!FPGAtoAD_clk_in)
begin
n <= 8'h0;
FPGA_r_state <= R_start;
to_cnt <= 26'd0;
FPGAtoAD_clk_out <= 1'b1;
end
else
FPGA_r_state <= R_idel;
R_start:
if(FPGAtoAD_clk_in)
begin
FPGAtoAD_clk_out <= 1'b0;
FPGA_r_state <= R_GetD;
to_cnt <= 26'd0;
end
else if(to_cnt<=26'd1000)
begin
FPGAtoAD_clk_out <= 1'b0;
FPGA_r_state <= R_start;
to_cnt<= to_cnt +1'b1;
end
else
begin
to_cnt <= 26'd0;
FPGA_r_state <= R_Busy;
pre_state <=R_start;
end
R_GetD:
begin
n_buf <= n_add;
FPGAtoAD_clk_out <= 1'b1;
ADCdata[n] <= FPGAtoAD_data;
if(n == 8'h41)
begin
n <= 8'h0;
FPGA_r_state <= R_over;
end
else
begin
FPGA_r_state <= R_WaitD;
end
end
R_WaitD:
if(!FPGAtoAD_clk_in)
begin
n<=n_buf;
FPGA_r_state <= R_start;
to_cnt <= 26'd0;
end
else if(to_cnt<=26'd1000)
begin
to_cnt<= to_cnt +1'b1;
FPGA_r_state <= R_WaitD;
end
else
begin
to_cnt <= 26'd0;
FPGA_r_state <= R_Busy;
pre_state <=R_WaitD;
end
R_Busy: FPGAtoAD_clk_out <= 1'b1;//FPGA_r_state <= R_over;
R_over:
begin
n <= 8'h0;
to_cnt <= 26'd0;
FPGAtoAD_clk_out <= 1'b1;
end
default:
FPGA_r_state <= R_idel;
endcase
end
else if(FPGAtoAD_rw == 2'b01)
begin
case(FPGA_w_state)
W_idel:
begin
FPGAtoAD_clk_out <= 1'b1;
FPGAtoAD_state <= 5'd0;
FPGA_w_state <= w_start;
end
w_start: //确认AD模块空闲
begin
FPGAtoAD_clk_out <= 1'b1;
FPGAtoAD_state <= 5'd0;
if(to_cnt< 26'd1000) //ensure AD MOD free
begin
if(!FPGAtoAD_clk_in)
begin
FPGA_w_state <= w_adbusy;
pre_state <=w_start;
to_cnt <= 26'd0;
end
else
to_cnt<=to_cnt+1'b1;
end
else
begin
FPGA_w_state <= w_sclk_L;
to_cnt <= 26'd0;
end
end
w_adbusy:
FPGA_w_state <= W_idel;
w_sclk_L: //确认AD模块空闲后拉低FPGA写时钟
begin //并等待AD模块时钟拉低
FPGAtoAD_clk_out <= 1'b0;
FPGAtoAD_state <= FPGAtoAD_commd;
if(!FPGAtoAD_clk_in) //AD模块时钟拉低后等待数据读取
begin
//FPGA_w_state <= w_sdata;
to_cnt <= 26'd0;
FPGA_w_state <= w_buftim; //
end
else if(to_cnt<outime)
begin
FPGA_w_state <= w_sclk_L;
to_cnt <= to_cnt+1'b1;
end
else
begin
FPGA_w_state <= w_adbusy;
pre_state <=w_sclk_L;
to_cnt <= 26'd0;
end
end
w_buftim:
begin
FPGAtoAD_clk_out <= 1'b0;
FPGAtoAD_state <= FPGAtoAD_commd;
FPGA_w_state <= w_sdata;
end
w_sdata:
begin
FPGAtoAD_clk_out <= 1'b1;
FPGAtoAD_state <= FPGAtoAD_commd;
if(FPGAtoAD_clk_in)
begin
FPGA_w_state <= w_sover;
to_cnt <= 26'd0;
end
else if(to_cnt<26'd1010)
begin
FPGA_w_state <= w_sdata;
to_cnt <= to_cnt+1'b1;
end
else
begin
FPGA_w_state <= w_adbusy;
pre_state <=w_sdata;
to_cnt <= 26'd0;
end
end
w_sover:
begin
to_cnt <= 26'd0;
FPGAtoAD_clk_out <= 1'b1;
FPGAtoAD_state <= 5'd0;
n <= 8'h0;
end
//FPGA_w_state <= W_idel;
default:
begin
FPGAtoAD_clk_out <= 1'b1;
FPGAtoAD_state <= 5'd0;
FPGA_w_state <= W_idel;
end
endcase
end
else
begin
FPGA_r_state <= R_idel;
FPGA_w_state <= W_idel;
n <= 8'h0;
to_cnt <= 26'd0;
FPGAtoAD_clk_out <= 1'b1;
FPGAtoAD_state <= 5'd0;
end

复制代码

Gshop · 发表于 2019-7-13 17:18:50

补充说明一下：
计数的是n
其实原来的计数我是简单的通过n<= n+1'b1;
这个语句来实现的，但是计数有问题我才改成现在这样的
原来的程序没有
wire [7:0] n_add;
reg [7:0] n_buf;
这两个参数，但是计数还是有问题
除此之外，我写的部分程序利用计数来实现时序控制，有时也是会有时序抖动的问题，估计问题也是出在计数输出结果不对。
求大牛指点

CJYCJY · 发表于 2019-7-13 23:06:32

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简单的计数程序输出结果总是不对，求大牛帮忙

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