主程序:
module Data_Select(
select_in,
data_out
);
input [1:0] select_in;
output reg [3:0] data_out;
always@(select_in)
begin
case (select_in)
2'b00:data_out<=4'b0001;
2'b01:data_out<=4'b0010;
2'b10:data_out<=4'b0100;
2'b11:data_out<=4'b1000;
default: ;
endcase
end
endmodule
testbench:
`timescale 1 ns/ 1 ns
module Data_Select_vlg_tst();
reg [1:0] select_in;
// wires
wire [3:0] data_out;
Data_Select i1 (
.data_out(data_out),
.select_in(select_in)
);
initial
begin
select_in<=2'b00;
#100 select_in<=2'b01;
#100 select_in<=2'b11;
#100 select_in<=2'b10;
#100 select_in<=2'b00;
#100 $stop;
end
endmodule
运行仿真后为什么会出现如图这样的结果呢?波形出不来呀!!
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