FPGA报错，添加了时钟时序，还有这个报错怎么解决？

banshan

Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command.
        Critical Warning (332169): From sys_clk (Rise) to sys_clk (Rise) (hold)
Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command.
        Critical Warning (332169): From sys_clk (Rise) to sys_clk (Rise) (hold)
        Critical Warning (332169): From sys_clk (Rise) to sys_clk (Rise) (hold)
Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command.
        Critical Warning (332169): From sys_clk (Rise) to sys_clk (Rise) (hold)
        Critical Warning (332169): From sys_clk (Rise) to sys_clk (Rise) (hold)
Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command.
        Critical Warning (332169): From sys_clk (Rise) to sys_clk (Rise) (hold)
        Critical Warning (332169): From sys_clk (Rise) to sys_clk (Rise) (hold)

banshan

没有人回复，自己顶一个，可别沉下去

QinQZ

也有可能是添加的时序约束不完整导致的，不过一般警告不影响功能的话可以不用管

banshan

QinQZ 发表于 2018-12-21 08:40
也有可能是添加的时序约束不完整导致的，不过一般警告不影响功能的话可以不用管

你会不会呀