标题: Place 30-764和Place 30-99 这两个问题怎么解决啊？ [打印本页] 作者: VVSpecialJoeVV 时间: 2022-4-18 09:36
标题: Place 30-764和Place 30-99 这两个问题怎么解决啊？
我在HDMI显示的基础上，另外加了一条数据通路，额外用到了VDMA等，也自定了VIP，在480x272的LCD屏上能够正常完成，但是一旦变成720P，用HDMI显示，就出现了下面的问题，请问，这个问题怎么解决？
[Place 30-764] Unroutable Placement! RAMBs driven by regional clock buffers (BUFRs and BUFHs) need to be in the same clock region as the buffers. There are not enough free RAMB sites available in the clock region where some of the buffers are placed. Some of them are listed below.
target_detect_HW_i/axi_dynclk_0/U0/BUFR_inst (BUFR.O) is provisionally placed by clockplacer on BUFR_X0Y2
The above error could possibly be related to other connected instances. Following is a list of
all the related clock rules and their respective instances.
Clock Rule: rule_bufr_IoClkLds
Status: PASS
Rule Description: A BUFR driving any number of IOBs must be placed within the same clock region
target_detect_HW_i/axi_dynclk_0/U0/BUFR_inst (BUFR.O) is provisionally placed by clockplacer on BUFR_X0Y2
target_detect_HW_i/DVI_Transmitter_0/inst/serializer_b/OSERDESE2_Master (OSERDESE2.CLKDIV) is provisionally placed by clockplacer on OLOGIC_X0Y28
target_detect_HW_i/DVI_Transmitter_0/inst/serializer_b/OSERDESE2_Slave (OSERDESE2.CLKDIV) is provisionally placed by clockplacer on OLOGIC_X0Y27
target_detect_HW_i/DVI_Transmitter_0/inst/serializer_clk/OSERDESE2_Master (OSERDESE2.CLKDIV) is provisionally placed by clockplacer on OLOGIC_X0Y26
target_detect_HW_i/DVI_Transmitter_0/inst/serializer_clk/OSERDESE2_Slave (OSERDESE2.CLKDIV) is provisionally placed by clockplacer on OLOGIC_X0Y25
target_detect_HW_i/DVI_Transmitter_0/inst/serializer_g/OSERDESE2_Master (OSERDESE2.CLKDIV) is provisionally placed by clockplacer on OLOGIC_X0Y24
target_detect_HW_i/DVI_Transmitter_0/inst/serializer_g/OSERDESE2_Slave (OSERDESE2.CLKDIV) is provisionally placed by clockplacer on OLOGIC_X0Y23
target_detect_HW_i/DVI_Transmitter_0/inst/serializer_r/OSERDESE2_Master (OSERDESE2.CLKDIV) is provisionally placed by clockplacer on OLOGIC_X0Y22
target_detect_HW_i/DVI_Transmitter_0/inst/serializer_r/OSERDESE2_Slave (OSERDESE2.CLKDIV) is provisionally placed by clockplacer on OLOGIC_X0Y21
Clock Rule: rule_bufio_clklds
Status: PASS
Rule Description: A BUFIO driving any number of IOBs must be placed within the same bank. In V7, there
is at most one IO bank in each clock region so the SameClockRegion rule is sufficient to satisfy the
requirement.
target_detect_HW_i/axi_dynclk_0/U0/BUFIO_inst (BUFIO.O) is provisionally placed by clockplacer on BUFIO_X0Y1
target_detect_HW_i/DVI_Transmitter_0/inst/serializer_b/OSERDESE2_Master (OSERDESE2.CLK) is provisionally placed by clockplacer on OLOGIC_X0Y28
target_detect_HW_i/DVI_Transmitter_0/inst/serializer_b/OSERDESE2_Slave (OSERDESE2.CLK) is provisionally placed by clockplacer on OLOGIC_X0Y27
target_detect_HW_i/DVI_Transmitter_0/inst/serializer_clk/OSERDESE2_Master (OSERDESE2.CLK) is provisionally placed by clockplacer on OLOGIC_X0Y26
target_detect_HW_i/DVI_Transmitter_0/inst/serializer_clk/OSERDESE2_Slave (OSERDESE2.CLK) is provisionally placed by clockplacer on OLOGIC_X0Y25
target_detect_HW_i/DVI_Transmitter_0/inst/serializer_g/OSERDESE2_Master (OSERDESE2.CLK) is provisionally placed by clockplacer on OLOGIC_X0Y24
target_detect_HW_i/DVI_Transmitter_0/inst/serializer_g/OSERDESE2_Slave (OSERDESE2.CLK) is provisionally placed by clockplacer on OLOGIC_X0Y23
target_detect_HW_i/DVI_Transmitter_0/inst/serializer_r/OSERDESE2_Master (OSERDESE2.CLK) is provisionally placed by clockplacer on OLOGIC_X0Y22
target_detect_HW_i/DVI_Transmitter_0/inst/serializer_r/OSERDESE2_Slave (OSERDESE2.CLK) is provisionally placed by clockplacer on OLOGIC_X0Y21
Clock Rule: rule_mmcm_bufr_bufio
Status: PASS
Rule Description: An MMCM driving a BUFR/BUFIO must both be in the same clock region
target_detect_HW_i/axi_dynclk_0/U0/Inst_mmcme2_drp/mmcm_adv_inst (MMCME2_ADV.CLKOUT0) is provisionally placed by clockplacer on MMCME2_ADV_X0Y0
target_detect_HW_i/axi_dynclk_0/U0/BUFIO_inst (BUFIO.I) is provisionally placed by clockplacer on BUFIO_X0Y1
target_detect_HW_i/axi_dynclk_0/U0/BUFR_inst (BUFR.I) is provisionally placed by clockplacer on BUFR_X0Y2
Clock Rule: rule_mmcm_mmcm
Status: PASS
Rule Description: An MMCM driving an MMCM must be in the same CMT column, and they are adjacent to
each other (vertically), if the CLOCK_DEDICATED_ROUTE=BACKBONE constraint is NOT set
target_detect_HW_i/axi_dynclk_0/U0/Inst_mmcme2_drp/mmcm_adv_inst (MMCME2_ADV.CLKFBOUT) is provisionally placed by clockplacer on MMCME2_ADV_X0Y0
and target_detect_HW_i/axi_dynclk_0/U0/Inst_mmcme2_drp/mmcm_adv_inst (MMCME2_ADV.CLKFBIN) is provisionally placed by clockplacer on MMCME2_ADV_X0Y0
[Place 30-99] Placer failed with error: 'IO Clock Placer failed'
Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.
[Common 17-69] Command failed: Placer could not place all instances